Abstract: A method for manufacturing integrated circuits using opaque field, phase shift masking. One embodiment of the invention includes using a two mask process. The first mask is an opaque-field phase shift mask and the second mask is a single phase structure mask. A phase shift window is aligned with the opaque field using a phase shift overlap area on the opaque field. The phase shift mask primarily defines regions requiring phase shifting. The single phase structure mask primarily defines regions not requiring phase shifting. The single phase structure mask also prevents the erasure of the phase shifting regions and prevents the creation of undesirable artifact regions that would otherwise be created by the phase shift mask.
Abstract: The present invention relates to a telecommunications system and method for connecting to a network and for routing data of a plurality of different data types between the network and subscriber terminals of the telecommunications system. The subscriber terminals are connectable to a central terminal of the telecommunications system via a transmission medium, the telecommunications system providing a number of communication channels arranged to utilize the transmission medium for transmission of data between the central terminal and the subscriber terminals. The telecommunications system comprises a transmitter having first transmission processing logic for employing a first transport mechanism to transmit data and second transmission processing logic for employing a second transport mechanism to transmit data.
Abstract: Techniques are provided for extending the use of phase shift techniques to implementation of masks used for complex layouts in the layers of integrated circuits, beyond selected critical dimension features such as transistor gates to which such structures have been limited in the past. The method includes identifying features for which phase shifting can be applied, automatically mapping the phase shifting regions for implementation of such features, resolving phase conflicts which might occur according to a given design rule, and application of sub-resolution assist features within phase shift regions and optical proximity correction features to phase shift regions. In one approach, phase shift regions are laid out so that they extend around corners in a feature, and in one or more identified corners having greater process latitude, the phase shift regions are divided and assigned opposite phases in the corner.
Abstract: An apparatus for scaling an image composed of pixels by a scale factor is described. The apparatus includes a local image analyzer for identifying from among said pixels a target pixel and a set of pixels proximate to said target pixel and determining a type for the target pixel. The apparatus includes a linear interpolation function that is parameterized by a horizontal linear interpolation coefficient and a vertical linear interpolation coefficient. The apparatus includes an interpolation coefficient generator for defining the horizontal and vertical linear interpolation coefficients. The apparatus includes an image scaler for scaling said image in a neighborhood of the target pixel by the scale factor using the linear interpolation function with the horizontal linear interpolation coefficient and the vertical linear interpolation coefficient. A method of scaling a source image.
Abstract: A method and system for cutting a wafer comprising a conductive substrate attached to an array of integrated devices includes placing the wafer on a stage such as a movable X-Y stage including a vacuum chuck having a porous mounting surface, and securing the wafer during and after cutting by vacuum pressure through the pores. The wafer is cut by directing UV pulses of laser energy at the conductive substrate using a solid-state laser. An adhesive membrane can be attached to the separated die to remove them from the mounting surface, or the die can otherwise be removed after cutting from the wafer.
Abstract: A process uses two layers of polysilicon for fabricating high-density nonvolatile memory, such as mask ROM or SONOS memory, integrated with advanced peripheral logic on a single chip. The method includes covering a gate dielectric layer with a first layer of polysilicon in the array portion and in the non-array portion; covering the first layer of polysilicon with a layer of silicon nitride; using two masks for gate electrode formation in a first layer of polysilicon and bit line implant processes; depositing a dielectric material among the gate electrode structures to fill gaps among the gate structures; planarizing the deposited oxide; removing said layer of silicon nitride and applying a second layer of polysilicon material; patterning wordlines in the array portion over said gate electrode structures, and transistor gate structures in said non-array portion, and applying LDD, silicide and other logic circuit processes.
Abstract: A method for defining a full phase layout for defining a layer of material in an integrated circuit is described. The method can be used to define, arrange, and refine phase shifters to substantially define the layer using phase shifting. Through the process, computer readable definitions of an alternating aperture, dark field phase shift mask and of a complimentary mask are generated. Masks can be made from the definitions and then used to fabricate a layer of material in an integrated circuit. The separations between phase shifters, or cuts, are designed for easy mask manufacturability while also maximizing the amount of each feature defined by the phase shifting mask. Cost functions are used to describe the relative quality of phase assignments and to select higher quality phase assignments and reduce phase conflicts.
Abstract: A one transistor, non-volatile programmable switch comprises a first node and a second node coupled with corresponding circuit elements in an integrated circuit. A single, non-volatile programmable transistor having a drain coupled to one of the first node and second node, a source coupled to the other of the first node and second node, gate coupled to an energizing conductor, the data storage structure constitute the programmable switch. The non-volatile programmable transistor consists of a mask programmable ROM cell, or a charge programmable device, in which the data storage structure comprises a floating gate or a nitride layer, or other charge trapping layer, between oxides or other insulators.
Abstract: An apparatus generates addresses for circular address buffers in a memory, in which a higher boundary of a circular buffer is implied from the current address. This approach is applied alone, and in combination with circular buffers which rely on an implied lower boundary to improve memory usage and flexibility in the design of circular buffers for integrated circuits. The dual mode address generator comprises inputs that receive a current address A, an address offset M, a buffer length L and a control signal; and logic configured to compute a first memory address for a buffer with an implied lower boundary and a second memory address for a buffer with an implied higher boundary in response to A, M, and L. One of the first and second memory addresses is provided in response to the control signal.
Abstract: A method extends the use of phase shift techniques to complex layouts, and includes identifying a pattern, and automatically mapping the phase shifting regions for implementation of such features. The pattern includes small features having a dimension smaller than a first particular feature size, and at least one relatively large feature, the at least one relatively large feature and another feature in the pattern having respective sides separated by a narrow space. Phase shift regions are laid out including a first set of phase shift regions to define said small features, and a second set of phase shift regions to assist definition of said side of said relatively large feature. An opaque feature is used to define the relatively large feature, and a phase shift region in the second set is a sub-resolution window inside the perimeter of the opaque feature.
Abstract: The present invention provides a digit handling system and digit handling method for a subscriber terminal of a wireless telecommunications system, the subscriber terminal being arranged to have an item of telecommunications equipment connected thereto and being connectable to a central terminal of the wireless telecommunications system via a radio resource to enable a call to be routed between the item of telecommunications equipment and an exchange coupled to the central terminal. The digit handling system comprises a detector for detecting when the item of telecommunications equipment enters an off-hook state, a dial tone generator for generating a fake dial tone to the item of telecommunications equipment upon detection of the off-hook state, and a radio manager, responsive to detection of the off-hook state, for seeking acquisition of a communication channel of the radio resource over which to pass call data.
March 8, 2001
Date of Patent:
August 10, 2004
Airspan Networks, Inc.
Nicholas John David Forbes, Richard Mortimer Lamkin
Abstract: Mechanisms for use on designated ports in spanning tree protocol entities allow such ports to transition to a forwarding state on the basis of actual communication delays between neighboring bridges, rather than upon expiration of forwarding delay timers. The logic that manages transition of states in the spanning tree protocol entity identifies ports which are changing to a designated port role, and issues a message on such ports informing the downstream port that the issuing port is able to assume a forwarding state. The logic begins the standard delay timer for entry to the listening state and then the learning state, prior to assuming the forwarding state. However, when a reply from the downstream port is received, then the issuing port reacts by changing immediately to the forwarding state without continuing to await expiration of the delay timer and without traversing transitional listening and learning states.
Abstract: A method and a system by which a document image is analyzed for the purposes of establishing a searchable data structure characterizing ground-truthed contents of the document represented by the document image operates by segmenting a document image into a set of image objects, and linking the image objects with fields that store metadata. Image objects identified by segmenting the document image are grouped into subsets. The image objects are grouped according to characteristics suggesting that the image objects may have common ground-truthed metadata. By grouping the image objects into subsets, the image objects may be indexed to facilitate the ground-truthing process. In some embodiments, the index of representative image objects is presented to the user in a table form. A database of image objects with ground-truthed metadata is formed. Interactive tools and processes facilitate ground-truthing based on paired image objects and metadata.
June 13, 2002
Date of Patent:
July 27, 2004
Floyd Steven Hall, Jr., Cameron Telfer Howie
Abstract: Autonomous retransmission of data packets onto a network from a Network Interface Card level upon command from a host processor is support. Efficient FIFO buffering in an ASIC is retained. Uses for autonomous retransmission include hardware and software testing and in network management.
Abstract: A self-aligned, nonvolatile memory structure based upon phase change materials, including chalcogenides, can be made with a very small area on an integrated circuit. The manufacturing process results in self-aligned memory cells requiring only two array-related masks defining the bit lines and word lines. Memory cells are defined at intersections of bit lines and word lines, and have dimensions that are defined by the widths of the bit lines and word lines in a self-aligned process. The memory cells comprise structures including a selection device, a heating/barrier plate layer and a phase change memory element, vertically arranged at the intersections of the bit lines and word lines.
Abstract: Techniques are provided for extending the use of phase shift techniques to implementation of masks used for complex layouts in the layers of integrated circuits, beyond selected critical dimension features. The method includes identifying features for which phase shifting can be applied, automatically mapping the phase shifting regions for implementation of such features, resolving phase conflicts which might occur according to a given design rule, and application of assist features and proximity correction features. The method includes applying an adjustment to a phase shift mask pattern including a first and a second phase shift window, and a control chrome with a control width, and/or to a trim mask pattern having a trim shape with a trim width based upon one or both of a rule based correction and a model based correction to improve a match between a resulting exposure pattern and a target feature.
Abstract: A method for producing a computer readable definition of photolithographic mask used to define a target pattern is provided. The phase shift mask patterns include phase shift windows, and the trim mask patterns include trim shapes, which have boundaries defined by such sets of line segments. For a particular pair of phase shift windows used to define a target feature in a target pattern, each of the phase shift windows in the pair can be considered to have a boundary that includes at least one line segment that abuts the target feature. Likewise, a complementary trim shape used in definition of the target feature, for example by including a transmissive region used to clear an unwanted phase transition between the particular pair of phase shift windows, includes at least one line segment that can be considered to abut the target feature.
Abstract: A sense amplifier inverts the output from the pass transistor to control a pre-charge transistor. The combination of the inverter and pre-charge transistor pre-charges the output to a level just below the flip level of the following data latch circuit. If the data cell read is a low threshold cell (conductive or “1”), the output level does not significantly change, and the data is rapidly latched and read. If the data cell is a high threshold cell (non-conductive or “0”), the pass transistor shuts off and the output is pulled up above the flip level of the data latch circuit through a pull-up path. The pre-charge level is near the flip level, so the output does not have to be pulled up very far, thus reading a “0” is also fast. In one embodiment, the pull-up transistor is a p-channel MOSFET with the gate grounded, thus providing more constant current than a diode-connected configuration.
Abstract: A process uses two layers of polysilicon for fabricating high-density nonvolatile memory, such as mask ROM or SONOS memory, integrated with advanced peripheral logic on a single chip. The method includes covering a gate dielectric layer with a sacrificial layer of silicon nitride; using a masks for defining line structures in the layer of silicon nitride for the bit line implant processes; depositing a dielectric material among the line structures to fill gaps among the line structures; planarizing the deposited oxide and said layer of silicon nitride; removing the silicon nitride and applying a layer of polysilicon material; patterning wordlines in the array portion, and transistor gate structures in said non-array portion, and applying LDD, silicide and other logic circuit processes.
Abstract: An improvement to the spanning tree protocol provides for identifying a port on the bridge in the alternate port role which qualifies as a candidate root port. Upon an event causing a topology change resulting in a particular port changing from the candidate root port role to the root port role and the previous root port changing to the designated port role, the process allows the previous root port to have the forwarding state without requiring transition through the listening and forwarding states. Qualification as a suitable candidate root port according is based upon propagating a message from the root bridge, such as a bridge protocol data unit (“BPDU”) message, carrying the identifier of the port on the root bridge from which the message originates. Logic in the bridges is able to identify the branch of the tree from which the message originates, and to select the candidate root port in response to the branch information.