Abstract: An improvement to the spanning tree protocol provides for identifying a port on the bridge in the alternate port role which qualifies as a candidate root port. Upon an event causing a topology change resulting in a particular port changing from the candidate root port role to the root port role and the previous root port changing to the designated port role, the process allows the previous root port to have the forwarding state without requiring transition through the listening and forwarding states. Qualification as a suitable candidate root port according is based upon propagating a message from the root bridge, such as a bridge protocol data unit (“BPDU”) message, carrying the identifier of the port on the root bridge from which the message originates. Logic in the bridges is able to identify the branch of the tree from which the message originates, and to select the candidate root port in response to the branch information.

Abstract: A one transistor, non-volatile programmable switch is less complex and requires less area than prior art devices. The programmable switch is used in an integrated circuit and comprises a first node and a second node coupled with corresponding circuit elements in the integrated circuit. A single, non-volatile programmable transistor having a drain coupled to one of the first node and second node, a source coupled to the other of the first node and second node, gate coupled to an energizing conductor, the data storage structure constitute the programmable switch. The non-volatile programmable transistor consists of a mask programmable ROM cell, or a charge programmable device, in which the data storage structure comprises a floating gate or a nitride layer, or other charge trapping layer, between oxides or other insulators.

Abstract: An asymmetric multilevel memory cell provides an inhibited source read current. The inhibited source read current dramatically reduces the likelihood of a cell type misread error for a memory array comprising multilevel cells. The method for fabricating the asymmetric multilevel memory cell comprises a source only implant, formation of a spacer on the drain side of the gate prior to source/drain implant, and the resultant formation of an offset region disposed between the channel and the drain. The offset region is not controlled by the gate voltage. The drain current at 1.5 volts is more than 3.5 times larger than the source current at 1.5 volts for spacer width of 0.12 micrometers. Asymmetric multilevel memory cells in a memory array, where the cells have a common source configuration, are accurately read in one direction because neighboring cells on the word line have substantially lower source current than the read cell drain current.

Abstract: Techniques are provided for extending the use of phase shift techniques to implementation of masks used for complex layouts in the layers of integrated circuits, beyond selected critical dimension features such as transistor gates to which such structures have been limited in the past. The method includes identifying features for which phase shifting can be applied, automatically mapping the phase shifting regions for implementation of such features, resolving phase conflicts which might occur according to a given design rule, and application of sub-resolution assist features within phase shift regions and optical proximity correction features to phase shift regions. Both opaque field phase shift masks and complementary binary masks defining interconnect structures and other types of structures that are not defined using phase shifting, necessary for completion of the layout of the layer are produced.

Abstract: Techniques are provided for extending the use of phase shift techniques to implementation of masks used for complex layouts in the layers of integrated circuits, beyond selected critical dimension features such as transistor gates to which such structures have been limited in the past. The method includes identifying features for which phase shifting can be applied, automatically mapping the phase shifting regions for implementation of such features, resolving phase conflicts which might occur according to a given design rule, and application of sub-resolution assist features within phase shift regions and optical proximity correction features to phase shift regions. Both opaque field phase shift masks and complementary binary masks defining interconnect structures and other types of structures that are not defined using phase shifting, necessary for completion of the layout of the layer are produced.

Abstract: An optical system modifies the optical orientation of the individual sources of a laser diode array so that the illumination provided by said individual sources may be combined into a single target location, while providing illumination at said target with the brightness of the individual sources. A first set of uniformly-spaced parallel light beams, said parallel beams defining a horizontal plane, is repositioned into a second set of uniformly-spaced parallel light beams, also defining a second horizontal plane but propagating in a direction perpendicular to the original light beams, with said second horizontal plane offset from said first horizontal plane, while the relative orientation of the high-brightness and low-brightness axes of said light beams with respect to the horizontal is interchanged. Three transformers are used to accomplish this reorientation.

Abstract: A method and an integrated circuit for performing a soft program after erase provides efficient convergence of over-erased floating gate memory cells disposed in bit lines. The soft program is applied to successive subject bit lines. The BLISP method includes selection of a selected bit line and applying the soft program to a subject bit line corresponding to the selected bit line. For integrated circuits having no defective bit lines, the subject bit lines comprise the selected bit lines. The BLISP method is adapted for low current consumption compared to bulk soft programming methods. In some embodiments, the integrated circuit includes defective bit lines. For these integrated circuits, the selection of the selected bit line includes indicating a bit line type corresponding to the selected bit line. The defective bit lines are logically replaced by redundant bit lines so that the soft program is applied to conforming selected bit lines and redundant bit lines corresponding to defective bit lines.

Abstract: A dual channel microwave sensor employs single sideband Doppler techniques in innumerable vibration, motion, and displacement applications. When combined with an active reflector, the sensor provides accurate range and material thickness measurements even in cluttered environments. The active reflector can also be used to transmit multi-channel data to the sensor. The sensor is a homodyne pulse Doppler radar with phasing-type Doppler sideband demodulation having a 4-decade baseband frequency range. Ranging is accomplished by comparing the phase of the Doppler sidebands when phase modulated by an active reflector. The active reflector employs a switch or modulator connected to an antenna or other reflector. In one mode, the active reflector is quadrature modulated to provide SSB reflections.

Abstract: An architecture for an integrated circuit with in-circuit programming, allows for dynamically altering the in-circuit programming instruction set itself; as well as other software stored on the chip. The architecture is based on a microcontroller on an integrated circuit having two or more banks of embedded non-volatile memory arrays which store instructions, including an in-circuit programming instruction set. Using a control program stored on the device, the device interactively establishes an in-circuit programming exchange with a remote partner, and updates data and software, including the in-circuit programming instruction set, when needed.

Abstract: An improved word line boost circuit suitable for use on integrated circuits such as flash memory devices includes a two step boosting circuit with a floating circuit node. A first circuit provides an initial boost of the output voltage from a precharged voltage. Part of the first circuit is floated, lessening a load on a second circuit. Then, the second circuit provides a second boost of the output voltage with increased power efficiency. A time delay separates the onset of the second boosting operation from the onset of the first boosting operation so as to define a two-step boost.

Abstract: A method for performing design rule checking on OPC corrected or otherwise corrected designs is described. This method comprises accessing a corrected design and generating a simulated image. The simulated image corresponds to a simulation of an image which would be printed on a wafer if the wafer were exposed to an illumination source directed through the corrected design. The characteristics of the illumination source are determined by a set of lithography parameters. In creating the image, additional characteristics can be used to simulate portions of the fabrication process. However, what is important is that a resulting simulated image is created. The simulated image can then be used by the design rule checker. Importantly, the simulated image can be processed to reduce the number of vertices in the simulated image, relative to the number of vertices in the OPC corrected design layout.

Abstract: A bi-static radar configuration measures the time-of-flight of an RF burst using differentially-configured sampling receivers. A precise differential measurement is made by simultaneously sampling a reference signal line and a free-space time-of-flight RF burst signal using separate sampling receivers having common sample timing. Two alternative sample timing systems may be used with the sampling receivers: (1) a swept delay using a delay locked loop (DLL), or (2) two precision oscillators slightly offset in frequency from each other. The receiver outputs are processed into a PWM signal to indicate antenna-to-antenna time-of-flight range or to indicate material properties. Applications include robotics, safety, material thickness measurement, material dielectric constant measurement, such as for fuel or grain moisture measurement, and through-tank fill-level measurement.

Abstract: A dither oscillator randomly modulates the instantaneous phase of a precision radar PRF oscillator. Radar spectral emission lines occurring at multiples of a transmit PRF oscillator are spread by the phase modulation, resulting in a continuous noise-like spectrum for reduced interference. The dither oscillator is based on a CMOS logic inverter and has adjustable coherence. The transition times of the PRF clock are decreased to 100 ps using negative resistance in an emitter follower to help injection-lock an RF oscillator to the PRF clock. Applications include spread-spectrum radar sensors operating in the crowded ISM bands, such as robotic and automotive pulse-echo rangefinders.

Abstract: Systems and methods are described for providing an array of buried transistor cells with at least one contact array structure. A contact array structure for a buried type transistor array includes a first diffusion bit line coupled to the plurality of transistors; a first plurality of contacts coupled to the source diffusion bit line; and a first conductor coupled to the first plurality of contacts. The systems and methods provide advantages in that the diffusion line resistance is reduced, the read current and speed are reduced, and the voltage-time distribution is tightened when writing by hot electron programming.

Abstract: An ESD protection structure for protecting an internal circuit comprising a primary protection device, a secondary protection device, and a substrate pickup is presented. The primary protection device and secondary protection device share a common source, and this common source implementation lowers the trigger voltage of the primary protection device to be about the same as the trigger voltage of the secondary protection device, thereby eliminating the need to use an isolation resistor between the primary and secondary protection devices.

Abstract: A constant false alarm rate (CFAR) detector prevents false radar triggers due to RF interference by proportionally increasing the radar detection threshold as interference increases. The radar operates with a randomized PRF, which randomizes detected RF interference while maintaining echo signal coherence. Post-detection filters provide a signal channel and an interference channel. The interference channel augments the threshold of the signal threshold detector. The interference channel gain can be adjusted to ensure the detection threshold is always higher than noise in the signal channel, thereby eliminating false alarms due to RF interference. Accordingly, the CFAR detector eliminates a major false alarm nuisance, particularly in radar security sensors. Applications for the low-cost system include indoor and outdoor burglar alarms, automotive security alarms, home and industrial automation, robotics, and vehicle proximity sensors.

Abstract: A single-wire time-domain reflectometer (TDR) combines the best performance features of prior art “electronic dipsticks” in a high accuracy implementation that allows tank penetration though a small opening. A wire-horn structure is employed to launch TDR pulses onto a single wire transmission line, wherein the horn wires can be flexed inwards so the dipstick structure can be inserted through a small tank opening. Once inside the tank, the horn wires flex to their normal state to provide a controlled reference reflection while simultaneously providing high coupling efficiency to the dipstick. The TDR system determines the fill-level of a tank by measuring the time difference between a reflection created at the wire-horn, which all is at the top of a tank, and a reflection from a material in the tank. The TDR employs automatic time-of-peak (TOP) detectors and incorporates a 2-diode sampler, a low-aberration pulse generator, and a 0.001% accurate timebase.

Abstract: A method and apparatus for performing an operation on hierarchically described integrated circuit layouts such that the original hierarchy of the layout is maintained is provided. The method comprises providing a hierarchically described layout as a first input and providing a particular set of operating criteria corresponding to the operation to be performed as a second input. The mask operation, which may include operations such as OPC and logical operations such as NOT and OR, is then performed on the layout in accordance with the particular set of operating criteria. A first program data comprising hierarchically configured correction data corresponding to the hierarchically described layout is then generated in response to the layout operation such that if the first program data were applied to the flattened layout an output comprising data representative of the result of performing the operation on the layout would be generated.

Abstract: A hearing analyzer, and a user-operated, user-calibrated audiological test system which comprises software, a calibrator, and specified headphones. The frequency response of the headphones is measured. The soundcard of a computer is used to generate audiological test signals, and either the actual output level of those signals or the analysis of results is compensated by software to the frequency response of the headphones. The calibrator allows an accurate calibration level to be established for the soundcard output. The software provides for using the method of adjustment test procedure to perform several audiological tests.

Abstract: A data processing unit comprises an input section 1 for inputting first data from the outside, an operation section 2 for operating the first data inputted therefrom, to generate second data, a memory section 3 for storing the second data, an output section 4 for outputting the second data stored in the memory section to the outside, and a control section 5 for controlling the memory section to enable storing and outputting of the second data.