Abstract: A method and apparatus for creating a phase shifting mask and a structure mask for shrinking integrated circuit designs. One embodiment of the invention includes using a two mask process. The first mask is a phase shift mask and the second mask is a single phase structure mask. The phase shift mask primarily defines regions requiring phase shifting. The single phase structure mask primarily defines regions not requiring phase shifting. The single phase structure mask also prevents the erasure of the phase shifting regions and prevents the creation of undesirable artifact regions that would otherwise be created by the phase shift mask. Both masks are derived from a set of masks used in a larger minimum dimension process technology.

Abstract: A range gated microwave motion sensor having adjustable minimum and maximum detection ranges with little response to close-in false alarm nuisances such as insects or vibrating panels. The sensor resolves direction of motion and can respond to target displacement in a selected direction and through a selected distance, in contrast to conventional hair-trigger motion sensors. A constant false alarm rate (CFAR) detector prevents false triggers from fluttering leaves, vibrating machinery, and RF interference. The sensor transmits an RF pulse and, after a modulated delay, mixes echo pulses with a mixer pulse. Thus, the echo pulses are modulated at the mixer output while transmit and mixer pulse artifacts remain unmodulated and easily filtered from the output. Accordingly, the sensor only responds to echoes that fall within its minimum and maximum range-gated region, and not to close-in or far-out objects.

Abstract: A method and apparatus for creating a phase shifting mask and a structure mask for shrinking integrated circuit designs. One embodiment of the invention includes using a two mask process. The first mask is a phase shift mask and the second mask is a single phase structure mask. The phase shift mask primarily defines regions requiring phase shifting. The single phase structure mask primarily defines regions not requiring phase shifting. The single phase structure mask also prevents the erasure of the phase shifting regions and prevents the creation of undesirable artifact regions that would otherwise be created by the phase shift mask. Both masks are derived from a set of masks used in a larger minimum dimension process technology.

Abstract: A single-antenna short-range radar transceiver emits 24 GHz RF sinewave packets and samples echoes with strobed timing such that the illusion of wave propagation at the speed of sound is observed, thereby forming an ultrasound mimicking radar (UMR). A 12 GHz frequency-doubled transmit oscillator is pulsed a first time to transmit a 24 GHz harmonic burst and pulsed a second time to produce a 12 GHz local oscillator burst for a sub-harmonically pumped, coherently integrating sample-hold receiver (homodyne operation). The time between the first and second oscillator bursts is swept to form an expanded-time replica of echo bursts at the receiver output. A random phase RF marker pulse is interleaved with the coherent phase transmitted RF to aid in spectrum assessment of the radar's nearly undetectable emissions.

Abstract: A floating gate having a first and second end region, each of which are positioned adjacent to a corresponding lateral end of the floating gate. A middle region is positioned laterally towards a middle of the floating gate relative to the first and second end regions. The first end region, the middle region and the second end region are formed of a same material during a single fabrication step, and the middle region formed has a thickness which is less than a thickness of the first or second end regions. This invention further includes a method for forming a contoured floating gate for use in a floating gate memory cell.

Abstract: Output drivers do not generate current when the pull up and pull down circuits are producing control signals which are below the turn on thresholds. Accordingly, no noise is translated to the output of the device in this period of time. Accordingly, an initial drive interval is provided in which the pull up and pull down control signals are driven with higher current so that the corresponding signal changes at a higher rate of speed before it reaches the turn on thresholds. Near the turn on thresholds, the rate of change of the pull up and pull down control signals is controlled to minimize noise during the transition and thereafter.

Abstract: This invention relates to sensing single and multiple bit non-volatile memories to determine what value is represented, by sensing both the source and drain of the cell being read. Sensing of threshold voltages is employed as an alternative to current sensing. A reference cell or miniarray is used as an input to differential sensing amplifier. The other input sensed is the threshold voltage of the cell being read. By sensing both the source and drain of a selected memory cell, substantial gains in sensing small voltage differentials in memory cells operating at reduced voltages or storing multiple bits of data is achieved.

Abstract: A method increases endurance of an array of memory cells which have an endurance specified according to the number of change cycles that the memory cell can endure within a performance tolerance. The method is based on arranging the array into a plurality of sectors, and assigning a subset of addresses for storage of data structure expected to change a number of times that is sufficient to exceed the specified endurance of the memory cell in the array. A record is maintained indicating one of the plurality of sectors as a current sector, directing accesses using the subset of addresses to the current sector, counting changes executed to memory cells identified by the subset of addresses for the current sector, and changing the current sector to another one of the plurality of sectors when the count of changes exceeds the threshold.

Abstract: A bias circuit produces a common mode bias voltage that relies upon active, auto tracking feedback responsive to the reference voltage, such as analog ground, and to the common mode bias voltage to generate a common mode voltage for a differential amplifier. The bias circuit supports high-speed operation, and is stable with variations in temperature, manufacturing processes, and with shifts in the supply voltages. In one embodiment, the bias circuit comprises an operational amplifier and a feedback amplifier that has a common mode bias terminal coupled to the output of the operational amplifier and arranged in a feedback loop with the operational amplifier. The output of the operational amplifier is used as a common mode bias voltage for a differential amplifier.

Abstract: Low power event monitoring enabling logic allows wake up devices to maintain their proper functionality in the event of a momentary power loss, or in the event the operating system does not properly load upon power-up. The technology is particularly suited for use with network interface card supporting Wake-On-LAN functions. A component with low power enabling logic is provided for a system having power management resources responsive to power management event signals to switch to an operating state. The component comprises power logic having a first mode in which power consumption is limited to a first specified level and a second mode in which power consumption is limited to a second specified level higher than the first specified level. The component includes an interface to nonvolatile memory storing a control signal.

Abstract: A system for providing policy management in a network that includes nodes operating in multiple protocol layers and having enforcement functions. Multiple network devices, such as routers, remote access equipment, switches, repeaters and network cards, and end system processes having security functions are configured to contribute to implementation of policy enforcement in the network. By distributing policy enforcement functionality to a variety of network devices and end systems, a pervasive policy management system is implemented. The policy management system includes a policy implementation component that accepts policy, i.e. instructions or rules, that define how the network device should behave when confronted with a particular situation.

Abstract: A sequence of steps presents node-link representations on a display. The sequence includes a first step, a last step, and at least one intermediate step. The first step presents a first representation that represents a first node-link structure. The last step presents a last representation that represents a second node-link structure that is a modified version of the first node-link structure. Both node-link structures include a set of shared elements that include a moving element. The moving element is represented by features that have different positions in the first and last representations. Each intermediate step presents an intermediate representation that includes features representing a subset of the shared elements including the moving element, and each element in the subset is also represented by features in the first and last representations. The feature representing the moving element has object constancy through the sequence of steps.

Abstract: Two crystal oscillators are configured as a “plug-and-play” precision transmit-receive clock system that requires no calibration during manufacture. A first crystal oscillator generates a transmit clock and a second crystal oscillator generates a receive clock that operates at a small offset frequency &Dgr; from the transmit clock. A frequency locked loop regulates &Dgr; by regulating the frequency of the detected receive pulses from a radio, radar, laser, ultrasonic, or TDR system. The clock system further includes a wrong sideband reset circuit and a phase lock injection port. Applications include a timing system for automotive backup and collision warning radars, precision radar and laser rangefinders for fluid level sensing and robotics, precision radiolocation systems, and universal object/obstacle detection and ranging.

Abstract: A method and apparatus for the correction of integrated circuit layouts for optical proximity effects which maintains the original true hierarchy of the original layout is provided. Also provided is a method and apparatus for the design rule checking of layouts which have been corrected for optical proximity effects. The OPC correction method comprises providing a hierarchically described integrated circuit layout as a first input, and a particular set of OPC correction criteria as a second input. The integrated circuit layout is then analyzed to identify features of the layout which meet the provided OPC correction criteria. After the areas on the mask which need correction have been identified, optical proximity correction data is generated in response to the particular set of correction criteria. Finally, a first program data is generated which stores the generated optical proximity correction data in a hierarchical structure that corresponds to the hierarchical structure of the integrated circuit layout.

Abstract: A charge pump circuit which generates an output voltage at a selected level, but variations in the current supplied to the charge pump are limited, and variations in the output current generated by the charge pump are limited. The charge pump circuit is coupled to a power supply which has a supply voltage which varies over a specified range. It includes a first charge pump that generates a reference voltage higher than the supply voltage in response to the supply voltage. A circuit, coupled to the first charge pump and responsive to the reference voltage generates a regulated supply voltage. A second charge pump generates a controlled output voltage in response to the regulated supply voltage. The regulated supply voltage is used by pump clock drivers and as a pump reference supply for the second charge pump.

Abstract: An improved wear resistant bump contact is produced by the inclusion of small particles of hard materials in the conductive material of the contact bump, preferably by co-deposition at the time of electroplating of the bump bulk material. Desirable attributes of the small particles of hard material include small particle size, hardness greater than the hardness of the bulk material of the contact bump, compatibility with the plating conditions, and electrical conductivity. Nitride, borides, silicides, carbides are typical interstitial compounds suitable for use in satisfying these desirable attributes. In one preferred example, a nickel bulk material and silicon carbide particles are utilized. In one variation, the bump of metal-particle co-deposited material is coated by a thin cap layer of noble, non-oxidizing metal to prevent electrical erosion by arcing as contact is made and broken from the pad. Rhodium and ruthenium are suitable metals and can be electrodeposition over the composite bump structure.

Abstract: A new flash memory cell structure and operational bias approach for allowing programming operations significantly faster than prior approaches, is based on the use of band-to-band tunneling induced hot electron injection in cells to be programmed and on the use of triple-well floating gate memory structures. The method comprises inducing band-to-band tunneling current from the semiconductor body to one of the source and drain near the channel, and applying a positive bias voltage to the control gate to induce hot electron injection into the floating gate. The other of the source and drain terminals is floated, that is disconnected so that current does not flow through that terminal. The band-to-band tunneling current is induced by applying a reference potential to one of the source and drain sufficient to establish conditions for the band-to-band tunneling current.

Abstract: Support for priority and IP security packets, and other protocols at the network interface level and in conjunction with FIFO-based packet buffers is provided by allowing out of order processing of certain packets in the FIFO. The optimized character of FIFO for sequential transfer is maintained, while particular types of packets are processed out of order to achieve minimum latency and maximum data security in an intelligent network interface card. A buffer stores data packets in an order of receipt. Logic is included in the network interface to transfer packets out of the buffer according to the order of receipt, and according to the respective packet types so that packets having a particular packet type are transferred out of the order of receipt relative to packets having other packet types.

Abstract: A node-link structure laid out in a space with negative curvature, such as the hyperbolic plane, is mapped to a rendering space, such as the unit disk, beginning from a starting element that has both a parent and a child. Data identifying the starting element are obtained, such as based on user signals. The starting element can be located at a starting position in the unit disk. Then a set of other elements can be mapped, each reachable from the starting element by a path that leads only through elements in the set. Each element's position in the negatively curved space relative to a preceding element on its path and the position of the preceding element in the rendering space can be used to obtain the element's position in the rendering space. The positions in the unit disk can then be used to present a representation of the node-link structure.

Abstract: A triple well charge pump comprises a first transistor connected in a diode configuration having a first channel terminal, nominally the source, coupled to a first node, and the second channel terminal, nominally the drain, coupled to its gate and to a second node. A first capacitor has a first terminal coupled to the first node of the charge pump, and a second terminal adapted to receive a first clock signal. A second transistor has a first channel terminal coupled to the second node of the charge pump, and a second channel terminal coupled to its gate and to a third node. A second capacitor has a first terminal coupled to the second node, and a second terminal adapted to receive a second clock signal.