Abstract: A semiconductor transformer provides high frequency operation by forming the primary windings of the transformer around a section of magnetic material that has a hard axis that lies substantially parallel to the direction of the magnetic field generated by the primary windings. The core can also be formed to have a number of sections where the magnetic flux follows the hard axis through each section of the core.

Abstract: A multiport test jack that supports the testing of a number of individual telephone lines in an interface device, such as a network interface device or an optical line terminal, has a physical structure that is smaller in size than the size of a corresponding number of individual test jacks.

Abstract: An orientation sensor includes a measure of ferrofluid that moves as the orientation sensor moves. The movement of the ferrofluid, which lies over a number of coils, alters the magnetic permeability of the flux path around each coil. The orientation sensor determines a change in orientation by measuring a change in the voltage across each coil. The voltage across each coil changes as the inductance changes which, in turn, changes as the magnetic permeability of the flux path changes.

Abstract: The bow in a wafer that results from fabricating a large number of MEMS devices on the top surface of the passivation layer of the wafer so that a MEMS device is formed over each die region is reduced by forming a stress relief layer between the passivation layer and the MEMS devices.

Abstract: A scalable MEMS inductor is formed on the top surface of a semiconductor die. The MEMS inductor includes a plurality of magnetic lower laminations, a circular trace that lies over and spaced apart from the magnetic lower laminations, and a plurality of upper laminations that lie over and spaced apart from the circular trace.

Abstract: A copper-compatible fuse target is fabricated by forming a copper target structure at the same time that the copper traces are formed. After the copper target structure and the copper traces have been formed, a conductive target, such as an aluminum target, is formed on the copper target structure at the same time that conductive connection portions, such as aluminum pads, are formed on the copper traces. A trench is then etched around the copper target structure and conductive target to form a fuse target.

Abstract: The radio frequency (RF) impedance of a metal trace at gigahertz frequencies is reduced by forming the metal trace to have a base region and a number of fins that extend away from the base region. When formed in a spiral configuration having a number of loops, the metal trace forms an inductor with an increased quality factor (Q).

Abstract: A cellular telephone handset utilizes an electrically-steered directional antenna to increase the received signal strength when the handset is in a poor signal environment. As a result, the handset reduces the need for an end user to tilt and twirl their head to try and find the direction of the strongest signal strength.

Abstract: The scan flipflops on a semiconductor chip are stitched together to form one or more scan chains, located in one or more standard cell placement regions, after the optimal physical location of each scan flip-flop has been determined. As a result, the total length of the scan chain wires is substantially reduced, thereby reducing on-chip wiring congestion, flip-flop load capacitance, and flipflop power dissipation.

Abstract: An electrostatic discharge protection circuit (ESD protection circuit) provides ESD protection to all NMOS/PMOS transistors that are connected to the pins of a CMOS integrated circuit (IC). The ESD protection circuit will protect the CMOS IC against an ESD event, regardless of whether the CMOS IC is powered up, or powered down.

Abstract: A fuse target is fabricated in a copper process by forming a number of copper targets at the same time that the copper traces are formed. After the copper targets and the copper traces have been formed, metal targets, such as aluminum targets, are formed on the copper targets at the same time that metal bonding pads, such as aluminum bonding pads, are formed on the copper traces.

Abstract: The number of times that a non-volatile memory (NVM) can be programmed and erased is substantially increased by utilizing a localized heating element that anneals the oxide that is damaged by tunneling charge carriers when the NVM is programmed and erased. The program and erase voltages are also reduced when heat from the heating element is applied prior to programming and erasing.

Abstract: An electrically floating region is formed in the top surface of a semiconductor wafer to implement a radio frequency (RF) blocking structure. The RF blocking structure lies below the metal pads and traces that carry an RF signal in a metal interconnect structure to substantially reduces the attenuation of the RF signal.

Abstract: A micro-electromechanical (MEMS) relay decouples a flux path from magnetic actuation from the electrical path through the switch to eliminate signal degradations that result from fluctuations in the current around the core and, thereby the flux. In addition, the MEMS relay has a suspension structure that is independent of the core.

Abstract: A high voltage CMOS output buffer is constructed from low voltage CMOS transistors. The output buffer employs a series of unique CMOS inverter stages, each of which contains a switched PMOS transistor, one or more voltage drop blocks, and a switched NMOS transistor. The voltage drop blocks are composed of stacked PMOS transistors that are diode-connected—i.e., the PMOS gate terminal is connected to the PMOS drain terminal, and the PMOS body (N-well) terminal is connected to the PMOS source terminal. The diode-connected PMOS transistors reduce the voltage across the transistor gate oxide to a safe value, for all internal PMOS/NMOS transistors inside the CMOS output buffer.

Abstract: NPN and PNP bipolar junction transistors are formed on a wafer in a fabrication process that eliminates the heavily-doped buried layers and the lightly-doped epitaxial layer by forming back side collector contacts that are electrically connected to an interconnect structure on the top side of the wafer with through-the-wafer contacts.

Abstract: The time required to perform a passive voltage contrast test of an area of interest of a layer of interest is substantially reduced by digitizing a passive voltage contrast image to form contrast data that represents the image, and comparing the contrast data to computer aided design (CAD) data that defines the semiconductor device.

Abstract: A copper-topped die, which has exposed copper lines and pads, is utilized as the lower die in a stacked die structure. A non-conductive material is formed over the lower copper-topped die, and then selectively removed so that the non-conductive material covers and lies between the copper lines while none of the non-conductive material lies over the copper pads. An upper die is then attached to the non-conductive material.

Abstract: A method of forming capacitive structures in trenches which have been formed in a multilevel metal interconnect structure is disclosed. The method of forming the capacitive structures allows the capacitance of the multilevel metal interconnect structure to be adjusted, and thereby optimized, to respond to signals from devices that are formed on an underlying substrate.

Abstract: Detection and control circuitry are added to a conventional power supply to detect when a load, such as a portable electronic device, has been disconnected from the power supply and, when disconnected, interrupt a current path to the primary windings of a transformer within the power supply to substantially reduce the amount of reactive power that is consumed by the power supply.