Abstract: The variable latency associated with standard network forwarding devices is eliminated by forwarding timing packets through a network forwarding device with a constant delay. The network forwarding device of the invention time stamps timing packets that are received by the input ports with a predefined future time, and then outputs the timing packets from the output ports at the predefined time so that the transmission delay through the network forwarding device is the same from any port to any other port.
Abstract: A thin film resistor is formed to have very accurately defined dimensions which, in turn, allow the resistive value of the resistor to be very accurately defined. The resistor is formed on spaced-apart conductive pads which, in turn, are electrically connected to conductive plugs that are spaced apart from the resistor.
Type:
Grant
Filed:
December 19, 2005
Date of Patent:
December 15, 2009
Assignee:
National Semiconductor Corporation
Inventors:
Peter Johnson, Joseph A. De Santis, Richard Wendell Foote, Jr.
Abstract: A semiconductor sensor device is formed using MEMS technology by placing a thin layer of single-crystal silicon, which includes semiconductor devices, over a cavity, which has been formed in a semiconductor material. The thin layer of single-crystal silicon can be formed by forming the semiconductor devices in the top surface of a single-crystal silicon wafer, thinning the silicon wafer to a desired thickness, and then dicing the thinned wafer to form silicon layers of a desired size. The MEMS device can be used to implement a pressure sensor, microphone, temperature sensor, and a joystick.
Type:
Grant
Filed:
February 1, 2007
Date of Patent:
December 15, 2009
Assignee:
National Semiconductor Corporation
Inventors:
Gobi R. Padmanabhan, Visvamohan Yegnashankaran
Abstract: A micro-electromechanical (MEMS) actuator and relay are implemented using a copper coil and a magnetic core. The magnetic core includes a base section that lies within the copper coil, and a cantilever section that lies outside of the copper coil. The presence of a magnetic field in the coil causes the cantilever section to move horizontally away from a rest position, while the absence of the magnetic field allows the cantilever section to return to the rest position.
Type:
Grant
Filed:
May 25, 2007
Date of Patent:
October 13, 2009
Assignee:
National Semiconductor Corporation
Inventors:
Trevor Niblock, Peter J. Hopper, Roozbeh Parsa
Abstract: A unique number is formed with logic states from a static random access memory (SRAM), which is laid out to be balanced so that memory cells within the SRAM assume a non-random logic state when power is applied to the SRAM. The unique number is formed by grounding the word lines and bit lines before power is applied to the memory cells, applying power to the memory cells to assume the non-random logic state, reading the non-random logic states held by the memory cells, and forming the unique number from the logic states read from the memory cells.
Abstract: A micro-electromechanical (MEMS) actuator and relay are implemented using a copper coil and a magnetic core. The magnetic core includes a base section that lies within the copper coil, and a cantilever section that lies outside of the copper coil. The presence of a magnetic field in the coil causes the cantilever section to move vertically away from a rest position, while the absence of the magnetic field allows the cantilever section to return to the rest position.
Type:
Grant
Filed:
May 25, 2007
Date of Patent:
October 6, 2009
Assignee:
National Semiconductor Corporation
Inventors:
Trevor Niblock, Peter J. Hopper, Roozbeh Parsa
Abstract: The attenuation of an RF signal on a metal trace in a semiconductor die is substantially reduced by utilizing a number of RF blocking structures that lie on the surface of the substrate directly below the metal trace that carries the RF signal. The RF blocking structures include an isolation ring, and one or more doped regions that are formed inside the isolation ring.
Abstract: A method of forming an optical switch is disclosed. The optical switch is implemented with one or more cantilevered optical channels, which are formed in a flexible waveguide structure, and an actuator which is connected to the cantilevered optical channels, to position the cantilevered optical channels to direct an optical signal along one of a number of optical pathways.
Abstract: An Internet Group Multicast Protocol (IGMP) proxy provides network redundancy to prevent a severed or damaged line, or a malfunctioning router interface from denying services to the IGMP proxy by outputting the multicast group addresses that are received by the IGMP proxy to a first multicast interface that is electrically connected to a first router interface of a router, and to a second multicast interface that is electrically connected to a second router interface of the router.
Abstract: A power-on reset circuit includes a trigger circuit that indicates when a power supply has been turned on, and when the supply has reached a voltage level that is sufficient for normal chip operation. For chips that contain a crystal oscillator, the power-on reset circuit also includes logic that determines the duration of the crystal warm-up delay.
Abstract: A diode for alternating current (DIAC) electrostatic discharge (ESD) protection circuit is formed in a silicon germanium (SiGe) hetrojunction bipolar transistor (HBT) process that utilizes a very thin collector region. ESD protection for a pair of to-be-protected pads is provided by utilizing the base structures and the emitter structures of the SiGe transistors.
Abstract: A very, very low resistance micro-electromechanical system (MEMS) inductor, which provides resistance in the single-digit milliohm range, is formed by utilizing a single thick wide loop of metal formed around a magnetic core structure. The magnetic core structure, in turn, can utilize a laminated Ni—Fe structure that has an easy axis and a hard axis.
Type:
Grant
Filed:
June 21, 2007
Date of Patent:
March 24, 2009
Assignee:
National Semiconductor Corporation
Inventors:
Peter Johnson, Peter J. Hopper, Kyuwoon Hwang, Robert Drury
Abstract: A silicide bridged anti-fuse and a method of forming the anti-fuse are disclosed. The silicide bridged anti-fuse can be formed with a tungsten plug metalization process that does not require any additional process steps. As a result, anti-fuses can be added to an electrical circuit as trim elements for no additional cost.
Type:
Grant
Filed:
June 29, 2004
Date of Patent:
March 24, 2009
Assignee:
National Semiconductor Corporation
Inventors:
Charles A. Dark, William M. Coppock, Jeffery L. Nilles, Andy Strachan
Abstract: A chip which utilizes a silicon controlled rectifier (SCR) for ESD protection prevents a latchup condition from occurring when the SCR misfires and turns on during normal operation by utilizing a fuse in series with the SCR. The fuse allows the SCR to perform normally during an ESD event, but blows if the SCR misfires and attempts to pull a pin voltage down to the holding voltage.
Abstract: A multicasting network includes a number of routers that are connected together to form a ring. The routers include a source router that identifies incoming multicasting data packets, and forwards the multicasting data packets in both directions on the ring. The routers also include forwarding routers that identify incoming multicasting data packets, and forwards the multicasting data packets in only one direction on the ring. Further, each ring has two terminating routers that receive forwarded data packets on two external nodes, and accept forwarded data packets from only a first external node and not from a second external node. When a fault condition is detected that prevents data packets from being forwarded in a first direction on the ring, the routers down stream of the fault condition reconfigure themselves to receive forwarded data packets from the second direction.
Abstract: A static random access memory (SRAM) is laid out to be balanced so that, when power is applied to the SRAM, the cells of the SRAM have no preferred logic state. In addition, the SRAM is fabricated in a process the emphasizes mismatches so that each individual cell assumes a non-random logic state when power is applied.
Abstract: The width of the gate of a MOS transistor can be formed to have nanometer-width gate sizes, which are substantially less than the minimum feature size that can be photolithographically obtained with the method that is used to fabricate the MOS transistors, in a litho-less process by utilizing a conductive side wall spacer to form the gate of the MOS transistor.
Type:
Grant
Filed:
December 19, 2005
Date of Patent:
January 27, 2009
Assignee:
National Semiconductor Corporation
Inventors:
Gobi R. Padmanabhan, Visvamohan Yegnashankaran
Abstract: A MOS transistor and subsurface collectors can be formed by using a hard mask and precisely varying the implant angle, rotation, dose, and energy. In this case, a particular atomic species can be placed volumetrically in a required location under the hard mask. The dopant can be implanted to form sub-silicon volumes of arbitrary shapes, such as pipes, volumes, hemispheres, and interconnects.
Type:
Grant
Filed:
December 8, 2004
Date of Patent:
January 20, 2009
Assignee:
National Semiconductor Corporation
Inventors:
Peter J. Hopper, Vladislav Vashchenko, Philipp Lindorfer, Andy Strachan
Abstract: A primary server and a backup server that both run a RADIUS client in a cold start configuration share a single IP address that includes a limited number of message identifiers (MIDs). The primary server and the backup server each have a small number of fixed message identifiers. In addition, a large number of shared message identifiers are used by the primary server, and then used by the backup server a predetermined time after the primary server fails.
Type:
Grant
Filed:
March 13, 2007
Date of Patent:
December 30, 2008
Assignee:
Tellabs Petaluma, Inc.
Inventors:
Tsang Ming Jiang, Jhaanaki Krishnan, Weifang Yang
Abstract: An integrated data processing platform for processing a digital signal that includes a general purpose processor and a digital signal processor (DSP) module. The DSP module recovers digital data from a digital signal utilizing a sequence of DSP operations selected by the general purpose processor. The general purpose processor processes the digital data recovered by the DSP module, but is also available to perform general purpose tasks. A shared internal memory array selectively provides information to the DSP module and to the general purpose processor. The information stored in the internal memory array includes operands utilized in the execution of the DSP algorithm and selected instructions and data utilized by the general purpose CPU either for controlling the execution of the DSP algorithm or for executing its own general purpose tasks.
Type:
Grant
Filed:
January 20, 1999
Date of Patent:
October 20, 2009
Assignee:
National Semiconductor Corporation
Inventors:
Amos Intrater, Gideon Intrater, Moshe Doron, Lev Epstein, Maurice Valentaten, Israel Greiss