Abstract: A stress mode circuit is provided to generate a voltage that is either equal to a reference voltage or is a proportion of an external voltage (VCCEXT). The circuit includes two voltage divider circuits to provide the proportion voltage. Two differential amplifiers are provided to generate outputs corresponding to a comparison to the proportion voltage and the reference voltage. The outputs operate switches that couple the reference voltage or the proportion voltage to an output terminal.

Abstract: A semiconductor device having a ferroelectric film or a polycrystalline silicon gate, a humidity-resistant hydrogen barrier film, like TiN film, TiON film, etc., formed by hydrogen non-emission film forming method over the ferroelectric film or the polycrystalline silicon gate.

Abstract: A ferroelectric memory cell has an FET covered by an insulation layer and a ferroelectric capacitor located thereover. An interconnect couples an upper plate of the ferroelectric capacitor to a source/drain of the transistor. In a method of forming the cells, after the transistor is fabricated, the bottom electrode and ferroelectric dielectric are established, but the top capacitor electrode is not added until a further layer of insulation is added over the ferroelectric and windows are opened in it. One window is for the top electrode and another window is to one source/drain region of the FET.

Abstract: A counter circuit selectively generates counting sequences in binary and interleave counting modes. A counter is formed by 3 toggle flip-flops. The toggle signals are provided by a toggle control circuit which contains logic gates that are enabled or disabled based on the state of a mode select signal. In binary mode, output bits are permitted to be used to toggle higher order count stages. In interleave mode, the binary toggle signals are blocked, and another counter circuit counts toggle signals in the interleave sequence, which signals are passed by the toggle control circuit to toggle inputs of the main counter. The other counter circuit can be reset in response to a reset signal applied to a load enable input.

Abstract: A semiconductor device comprised of a transistor (TR) having a gate electrode, a source region and a drain region, and a ferroelectric capacitor formed above a local oxide film. The capacitor has a ferroelectric film, and upper and lower electrodes that sandwich the film therebetween. The lower electrode and the source region are connected to each other through a wiring or interconnection which is formed of a conductive reaction-preventing film with an Al wiring electrode stacked thereon. The conductive reaction-preventing film is formed of TiN, MoSi, W, etc. If an annealing treatment is carried out for the purpose of improving the characteristics of the semiconductor device or a final protection film is formed after the formation of the wiring electrode, the wiring electrode and the upper electrode do not react with each other. Thus, excellent characteristics of the ferroelectric film are obtained so that a highly integrated ferroelectric memory having high performance can be formed.

Abstract: In fabricating a contact window to source/drain electrode next to a gate electrode of an integrated circuit: (1) establishing a structure with a window over the source/drain region next to the gate electrode; (2) establishing a region of titanium silicide over the source/drain electrode and establishing a titanium nitride layer over the window and gate electrode; (3) establishing a layer of silicon nitride over the titanium nitride layer; (4) patterning the silicon nitride layer; (5) using the patterned silicon nitride layer as a mask to pattern the titanium nitride layer; (6) adding another silicon nitride layer to seal the gate electrode where it is not protected by titanium nitride; (7) opening a window over the electrode by an anisotropic etch; (8) widening the window with an isotropic etch, using the silicon nitride and titanium nitride as a protective barrier; and (9) adding contact material in said windows.

Abstract: A method for forming a ferroelectric capacitor for use an integrated circuit establishing one layer over another and then annealing the structure, using an oxygen or ozone anneal, after each layer is established. In particular, an ozone anneal is used after the establishment of a layer of ferroelectric material.

Abstract: Apparatus for the detection and correction of digitized image defects comprising a plurality of registers for storing a plurality of bits representative of a portion of digitized image comprising a central pixel and pixels surrounding the central one, means for reading out from said registers, through a sequence of reading operations, the level of the bits representative of said central pixel and of the pixels in the same row and column of said central pixel with a first read operation and the level of the bits representative of rows and columns of pixels adjacent to the central pixel and more and more far therefrom at each subsequent read operation, four sequencers receiving said bit levels and respectively analyzing a sector of the image portion located left, right, above and below the central pixel, the sequencers providing signals as result of such analysis to a decoder which outputs correction codes dependent on such analysis to a control unit of a visualization unit.

Abstract: A non-volatile ferroelectric memory having folded bit lines both reduces the size of the memory while also eliminating noise interference commonly associated with non-volatile ferroelectric memories having an open bit line architecture. The memory provides two pairs of coincident word and plate lines associated with each row, viz., plate line A paired with word line B, and plate line B paired with word line A. The plate line of a pair may overlie or underlie the word line of the pair, and one may have the same width or a different width as the other of the pair, but preferably the elements of the pair are generally aligned, and the elements of the other pair are aligned with themselves, the two pairs being distally spaced apart. Each cell in the row is connected at the appropriate location to a word line of one of the pairs and a plate line of the other pair. Therefore, the word line and plate line of any single cell are not coincident.

Abstract: In a memory construction using ferroelectric film, by embedding a capacitor formed by said ferroelectric film in a through hole bored in an interlayer insulating film formed on a semiconductor substrate, reliability of the wiring layer passing thereover so as to obtain a highly reliable semiconductor memory by reducing the step difference by said capacitor.

Abstract: A vacuum processing equipment is disclosed, which comprises a vacuum chamber and main and fore vacuum pumping mechanism for pumping down the vacuum chamber. The fore vacuum pumping mechanism includes a cooling means and a residual gas trapping means coupled to the cooling means. The cooling means is provided outside the vacuum chamber. The residual gas trapping means is provided in a zone of the vacuum chamber free from interference with the vacuum processing.

Abstract: A capacitor for a semiconductor structure is formed having a substrate, a stack of a buffer layer and a layer of ferroelectric material, and a top electrode. The capacitor can also have a layer of polysilicon between the substrate and the buffer layer. A method for forming the same, through establishing a substrate, a buffer layer and a layer of ferroelectric material, defining and annealing the buffer layer and layer of ferroelectric material, and establishing a top electrode, is also disclosed.

Abstract: The structural body of a ferroelectric capacitor C is located over a source region (23) between a gate electrode (22) and a local oxide film (26). The structural body has a ferroelectric film (29) and an upper electrode (30) and a lower electrode (31) for sandwiching the ferroelectric film (29), and is provided with a conductive oxide film (32) between the lower electrode (31) and the source region (23). The conductive oxide film (32) is ITO, ReO.sub.2, RuO.sub.2 or MoO.sub.3. If an oxygen anneal is conducted after forming the ferroelectric film (29) for the purpose of reforming crystallizability of the ferroelectric film (29), oxygen enters into the conductive oxide film (32) to some extent. As a result, the conductive oxide film (32) is further oxidized, and becomes a so-called oxide barrier or dummy layer.

Abstract: An operational amplifier circuit is composed of a differential amplifier circuit for delivering a signal which is obtained by amplifying a difference between voltage levels of two signals; a level shift circuit for shifting and delivering the voltage level of the signal delivered from the differential amplifier circuit; a first amplifier circuit for amplifying and delivering the signal from the level shift circuit; and a second amplifier circuit for amplifying and delivering the voltage level of the signal delivered from the differential amplifier circuit, and a CMOS output circuit whose conductive state is controlled in accordance with voltage levels of the signals delivered from the first and second amplifier circuits.

Abstract: A method for manufacturing a memory integrating a ferroelectric film, having properties such as excellent information rewriting times, breakdown voltage and leak current and the like, by forming a lower electrode sandwiching a ferroelectric material on a high concentration diffusion layer, such as source and drain regions, formed on a semiconductor substrate, and forming a polysilicon film between the electrode and the high concentration diffusion layer. A semiconductor device formed by the method of the present invention is also disclosed.

Abstract: A ferroelectric capacitor for use in integrated circuits and having an asymmetric operation. The capacitor has a bottom electrode, a layer of ferroelectric material over the bottom electrode, a dielectric spacer on the sides of the bottom electrode and ferroelectric material, and a top electrode over the layer of ferroelectric material. The bottom and top electrode are comprised of different materials. Alternatively, an ion implantation region is formed in the top surface of the layer of ferroeletric material. A method of forming the asymmetric ferroelectric capacitor is also disclosed.

Abstract: A semiconductor memory device has pairs of complementary bit lines connected to pairs of complementary data bus lines via transfer elements controlled by column lines. The bit lines are arranged so that mutually adjacent pairs of bit lines are connected to the same pair of data bus lines at a pair of common nodes. The transfer elements for each such mutually adjacent pair of bit lines are controlled by different column lines.

Abstract: A monolithic semiconductor integrated circuit-ferroelectric device is disclosed together with the method of manufacturing same. The ferroelectric device preferably consists of a layer of stable ferroelectric potassium nitrate disposed between electrical contacts positioned on opposite surfaces of the ferroelectric layer. The ferroelectric layer has a thickness of less than 110 microns, and preferably falling within a range of from 100 Angstrom units to 25,000 Angstrom units. The process of manufacturing the monolithic structure is multi-stepped and is particularly adapted for fabricating a potassium nitrate ferroelectric memory on a semiconductor integrated circuit.

Abstract: A ferroelectric capacitor for a memory device including a substrate, a bottom electrode and a top electrode. Between the bottom and top electrodes is either an alternating plurality of layers of ferroelectric material and intermediate electrodes or a plurality of layers of ferroelectric material. A method for forming the same through establishing one layer over the other is also disclosed.

Abstract: A ferroelectric capacitor for a ferroelectric memory device includes a substrate, a silicon dioxide layer, a palladium adhesion layer, a bottom electrode of platinum, a metal or an alloy, a ferroelectric material and a top electrode of platinum, a metal or an alloy.