Patents Represented by Attorney Mark J. Murphy
  • Patent number: 5187810
    Abstract: A mobile telecommunications system includes a plurality of base stations each being communicatable with a mobile station by radio. A telecommunications network accommodates the plurality of base stations for switching communications to the plurality of base stations. A system center is connected to the telecommunications network for selecting an optimum route on the basis of instantaneous traffic conditions. Any of the base stations sends to the mobile station base station data representative of the base station. When the mobile station sends a guidance request for requesting route guidance data, the telecommunications network reports the guidance request to the system center. The system center selects, in response to the guidance request, an optimum route matching instantaneous traffic conditions and transmits optimum route data representative of the optimum route to the mobile station over the telecommunications network.
    Type: Grant
    Filed: November 27, 1991
    Date of Patent: February 16, 1993
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Hiroto Yoneyama, Atushi Yashiki, Toshiyuki Kodama
  • Patent number: 5170242
    Abstract: A reaction barrier is formed at an interface region between adjacent layers of a multilayer composite integrated circuit by implanting one or more active ionic species at energies effective to place the ionic species at or near the interface. A further step may include annealing the structure formed above to promote efficacy of the reaction barrier.
    Type: Grant
    Filed: May 10, 1991
    Date of Patent: December 8, 1992
    Assignees: Ramtron Corporation, NMB Semiconductor Company, Ltd.
    Inventors: E. Henry Stevens, Masahiro Maekawa
  • Patent number: 5162890
    Abstract: In a multi-layered integrated memory circuit, a method for using sacrificial layers and insulating "sticks" is disclosed to provide a contact between two layers, where the contact does not short to an intervening layer. This invention provides this with minimal extra processing by using sacrificial layers with appropriate etch and etch stop properties. As these layers are etched, additional layers which alternate in the same conducting/insulating pattern are exposed. Each etch stops on either a conductive or insulative layer. A contact layer may then be deposited which connects the uppermost capacitor plate to the pass transistor of the memory cell.
    Type: Grant
    Filed: April 5, 1991
    Date of Patent: November 10, 1992
    Assignees: Ramtron Corporation, NMB Semiconductor Corporation
    Inventor: Douglas B. Butler
  • Patent number: 5142437
    Abstract: A ferroelectric capacitor for an integrated circuit includes a stack formed by a layer of a noble metal, a layer of a conducting oxide, a layer of a ferroelectric material, another layer of a conducting oxide and another layer of a noble metal. The capacitor can also have another layer of conducting oxide located over the top layer of noble metal and below the first layer of the noble metal. A method of forming the same through establishing one layer over the other and annealing each layer is also disclosed.
    Type: Grant
    Filed: June 13, 1991
    Date of Patent: August 25, 1992
    Assignee: Ramtron Corporation
    Inventors: Lee Kammerdiner, Maria Huffman, Manoochehr Golabi-Khoozani