Abstract: A dual path frequency synthesizer is disclosed which includes a controlled oscillator and a phase detector that determines the phase difference between an output signal of the controlled oscillator and a reference signal. The synthesizer also includes a charge pump that is coupled to the phase detector. The synthesizer includes a direct path loop filter which is coupled to a charge pump output. The synthesizer also includes an integrating path loop filter which is coupled to another charge pump output and which has substantially the same topology as the direct path loop filter. The direct path loop filter and the integrating path loop filter are substantially matched with one another. The charge pump pumps charge into the direct and integrating path loop filters in response to the phase difference between the reference signal and the output signal of the controlled oscillator as determined by the phase detector.

Abstract: A bias system is disclosed including a calibration bus to which a controller, a reference bias source, a master bias source, and first and second slave bias sources are coupled. The controller varies a control code sent over the calibration bus to the master bias source until a particular control code is found that causes the bias signal of the master bias source to equal a desired bias value which is provided by the reference bias source. The controller then sends the particular control code to the first and second slave bias sources to cause the first and second slave bias sources to generate a bias signal having the same desired bias value as the master bias source. Isolation between load circuits coupled to the first and second bias sources is thus enhanced while providing low noise, stable operation.

Abstract: A content management system is provided including a plurality of tables forming a tree-based hierarchy for storing information such as item information. An information retrieval interface is provided to facilitate retrieval of information from the tree-based table hierarchy. The number of cursors employed for retrieving information is dynamically variable with the number of tables in the hierarchy. Advantageously, the content management system permits tables to be added or appended to the initial tree-based table hierarchy after the database is created. The number of cursors is dynamically varied to accommodate the additional cursors needed to query the additional table or tables.

Abstract: A resilient mat is disclosed which provides cushioning and comfort to users standing thereon or otherwise contacting the mat. The mat includes a resilient gel inner layer surrounded by a support ring to which an upper cover member and a lower cover member are attached. The support ring exhibits stiffness greater than the stiffness of the upper and lower cover members so that adherence of the upper and lower cover members to the support ring is enhanced even after prolonged use. The upper and lower cover members can exhibit the same or different colors in particular embodiments. The upper and lower cover members also can exhibit anti-slip properties in selected embodiments.

Abstract: A method, computer product, and system for rewriting database without decreasing pushdownability is provided. First, a pushdown analysis of the query in its entirety is performed prior to the application of any query rewrite rules in order to establish a baseline on pushdownability for the query. The results of this analysis is stored with the internal query representation. After each rule is applied to rewrite a portion of a query, that rewritten portion is analyzed again for pushdownability. If pushdownability is not decreased, then the rewritten query remains and the internal representation of the query is updated to reflect the pushdownability of that portion. If pushdownability is decreased, then an undo operation is applied to the rewritten portion of the query to back out the effects of the rule and leave the query in the same state as before the rewrite. Finally, additional rewrite rules that are directed to the heterogeneous database environment are also provided.

Abstract: A personal computer includes a DC to DC converter which employs a dual function capacitive energy storage device at the output rail of the converter. The energy storage device provides both a transition control function and a bulk or output function. In this manner, the size and expense of a separate bulk capacitor is advantageously avoided. The converter includes a switching transistor coupled to a bulk inductor. The switching transistor exhibits a high frequency switching rate which is sufficiently high to permit the inductor to directly replenish the capacitive energy storage device thus enabling the converter to withstand both major and minor load fluctuations without loss of voltage regulation at the output rail.

Abstract: A method and apparatus which enhances computer system performance in systems that incorporate a cache system that requires a first non-zero number of wait states and a memory system write buffer that requires a second lesser number of wait states. The present invention reduces or eliminates wait states that are otherwise required during write cycles in prior art designs without adding cost. During burst writes to data entries cached in the second level cache system, a cache protocol is used whereby the cache controller snoops the respective addresses which are the target of the burst write cycle out of the cache system, i.e., marks the respective cache line invalid. This effectively eliminates the data from the cache at the beginning of the burst write cycle. Since the data has now been marked invalid, the cache line is not required to be updated.

Abstract: A modular computer bus providing a system for automatically maintaining proper bus termination. A module connector is located at on end of the bus. A switch device is located at the end of the bus as close as possible to the connector. The switch device couples a termination device to the end of the bus when the switch device is in an on state. The switch device is in the on state when no module is present in the connector and in an off state when a module, such as a processor module, is present in the connector. When the switch device is in the off state, the termination device is not coupled to the bus. Instead the end of the bus is terminated by a termination device on the module. Thus, computer bus is correctly terminated automatically when a module is inserted into or removed from the connector. Thus a bus structure is provided for implementing a bus standard while providing modularity and automatically maintaining proper bus termination.

Abstract: A switching power supply system for digitally measuring switching regulator current is provided. The switching power supply contains a pulse-width-modulator (PWM) controller for providing a series of constant voltage and constant frequency pulses to a tank circuit. The tank circuit provides a DC current to an electronic system. The duty cycle of the pulses, however, is varied, depending on the current drain of the electronic system. A counter is attached to an output of the PWM controller to provide a count that is relative to the width of an output pulse from the PWM controller. The count is provided to a power control system that utilizes the value of the count to determine the current output of the PWM controller. The power control system is also connected to the output of the tank circuit to monitor the voltage output of the PWM controller. The power control system utilizes the determined current output, and the monitored voltage output to determine the instantaneous power output of the PWM controller.

Abstract: A printed circuit board includes a multi-component mounting footprint for mounting one of several possible differently sized discrete component packages on the circuit board. The multi-component mounting footprint includes a first mounting pad which has two connection points for mounting a connector on one of two different sized components. The footprint also includes a second mounting pad which is symmetric to the first mounting pad. About the mounting pads are cut outs which prevent solder buildup when either one of two different sized components are mounted thereon.

Abstract: A portable computer is provided in which the consumption of power by the I/O ports of the computer is reduced. The processor of the computer distinguishes port I/O operations that require an actual data transfer from port I/O operations that do not require an actual data transfer. The I/O ports of the computer remain off until an I/O operation involving an actual data transfer at a particular port is required. When an I/O operation which requires an actual data transfer is encountered, then the appropriate port is powered up. In this manner, power consumption by the I/O ports of the computer is significantly reduced. Advantageously, the disclosed technique for reducing power consumption by the I/O ports of the computer is operating system independent. In this manner, the power management feature functions regardless of which particular operating system or application software is installed on the computer.

Abstract: There is disclosed a technique for constructing a printed circuit board assembly to provide solder joints with a uniform height. A solder mask is provided on the external surfaces of the printed circuit board to minimize the mount of conductive pad area that is exposed to solder. The solder mask includes a plurality of relatively small openings with a predetermined pattern to minimize the build up of solder, while insuring sufficient solder height to connect to the grounding component located on the chassis to insure adequate EMI protection. Preferably a polka dot pattern is used for certain conductive pads, while a single narrow strip or the solder mask opening configuration is used for rectangular pad configurations. Other configurations and patterns are also available to provide an adequate electrical connection while insuring uniform solder height.

Abstract: A handheld computer has a generally rectangular housing on a front side wall of which a display screen is operatively mounted. A row of toggle switches is also mounted on the front housing side wall, adjacent the display screen, the toggle switches being operatively connected to the computer circuitry within the housing. The toggle switches are manually depressible switch members having first and second non-momentary positions. The housing may be manually grasped in two perpendicular use orientations in each of which the user may reach and operate the toggle switches to control the operation of the computer. One of the toggle switches is operative, via the internal computer circuitry, to selectively rotate, through an angle of 90 degrees, the orientation of data generated on the screen so that in either of the first and second housing use orientations the screen data is in an upright viewing orientation relative to the user of the computer.

Abstract: A computer system is provided with the capability of protecting portions of the mass storage media therein from unauthorized access. The mechanism employed to protect portions of the mass storage media is advantageously operating system independent. Thus, the protection mechanism functions regardless of what operating system is installed or what particular application software is presently being executed. More particularly, the computer system includes a processor configured to execute code in an operational mode and in a system management mode. A mass storage device and a memory are coupled to the processor. At least one region of the mass storage device is designated as a protected region by the user or by the manufacturer. The computer system is configured to trap mass storage device I/O operations and, in response to a trapped mass storage device I/O operation, the processor enters a system management mode.

Abstract: A bus with selective burst ordering enables the implementation of computer systems that incorporate bus masters (e.g., processors, DMA controllers, LAN controllers, etc.) with dissimilar burst orders. The same bus supports devices which require or prefer differing burst orders for high bandwidth data transfers. Selective burst order is enabled through the use of a bus line which may be asserted by the current bus master. By asserting the corresponding signal, a current bus master indicates that sequential (rather than non-sequential) burst order will be used for data transfer. Specialized burst address generation logic enables a bus slave to generate, in the selected burst order, the low order bits of memory addresses for the data words implicitly addressed during a burst transfer.

Abstract: A memory mapping scheme for a computer system includes a number of slave devices attached to a system bus, which slave devices have partitioned among themselves a memory address storage system. The memory address storage system is, in turn, divided into a number of regions. The memory mapping scheme also includes a subsystem for mapping the regions, which subsystem includes a unique subtractive descriptor that disjunctively allows mapping of regions that reside on only one of a number of input/output channels connected to the system bus.

Abstract: A power supply including a detection and switch system for sensing either a uni-plane or a split-plane device connected to a socket and for providing one or two supply voltages, respectively. In one embodiment, a dual output regulator includes first and second regulators with corresponding first and second feedback circuits and comparators for regulating first and second outputs, respectively. A switch circuit connects the second feedback circuit to the comparator of the second regulator in split-plane mode for providing the second output. However, the switch circuit connects the first feedback circuit to the comparator of the second regulator in uni-plane mode where the two outputs are coupled together by a uni-plane device, so that the two outputs are regulated at the same level. A detection circuit monitors the output signals and controls the switch circuit depending upon whether a uni-plane or split-plane device is detected.

Abstract: A secondary cache memory system is disclosed for use in a portable computer that increases system performance while also conserving battery life. The secondary cache includes a cache controller for controlling the transfer to and from a cache memory, comprised of fast SRAM circuits. The cache controller includes a control and status register with at least three status bits to control power to the cache, and to insure that the data stored in the cache memory is coherent with system memory. A control and power management logic checks the contents of the control and status register, and monitors the activity level of the processor. When the processor is determined to be inactive, the control and power management logic turns off the cache by changing the state of a bit in the control and status register.

Abstract: A SCSI adapter card which provides one or more internal SCSI channels and includes connectors for an optional daughter card which provides an external SCSI connector. The daughter card is a parallel mezzanine style daughter board which provides modular and upgradable SCSI bus routing options. In the preferred embodiment, the adapter card includes two SCSI controllers which provide two internal SCSI channels. The daughter board can include up to 2 SCSI controllers for additional SCSI channels. The daughter board can reroute one or more of the internal SCSI channels to the external connector according to various SCSI routing options or can include one or more SCSI controllers for additional SCSI channels. In one embodiment, the daughter board does not include a SCSI controller, but rather serves to reroute one or more of the internal SCSI controllers to the external connector.

Abstract: A rechargeable battery pack including a microcontroller connected to a voltage measuring circuit and a current measuring circuit for measuring, respectively, the voltage across and the current flowing from a battery. Upon each expiration of a predefined time period during each discharge cycle of the battery, the microcontroller computes the product of the voltage, the current, and the length of the time period, thereby computing the energy expended by the battery over each period of time. An energy variable stored in a nonvolatile memory device associated with the microcontroller for representing the total amount of energy output by the battery over the life thereof is incremented by the computed energy. In one embodiment, a temperature sensing circuit measures the temperature of the battery and the instantaneous energy is adjusted by a temperature factor associated by the measured temperature before being used to increment the value of the energy variable.