Abstract: The present invention provides, in a computer chassis containing a substantially planar removable expansion card therein, the computer chassis having an opening therein allowing access to the expansion card, a plane of the expansion card substantially parallel with a plane of the opening, a support structure for the expansion card and a method of supporting the expansion card.

Abstract: A method and apparatus which synchronizes signals operating at different clock speeds with reduced synchronization latency. The present invention is preferably used in systems where a first logic portion operating at a first clock speed, referred to as a fast clock speed, interfaces to a second logic portion operating at a second, slower clock speed. A new slow clock is generated pseudo-synchronously from the fast clock using a phase locked loop (PLL) clock generator. The PLL multiplies the fast clock frequency up to the least common multiple (LCM) of the two frequencies to generate a base clock signal. The base clock is then divided down to form the slow clock signal. The PLL performs its operations in such a way that all three clocks have a fixed phase relationship. The rising edges of the base clock, fast clock, and slow clock line up at periodic points and are skewed at other periodic points.

Abstract: A system for detecting and locating errors in printed wire assemblies contained in a device with capabilities of performing a power on self test (POST) comprised of testing subroutines. The system monitors the device during execution of the POST. If a run error occurs during the POST, the system, through its monitoring, receives an indication of the run error. The system then delivers to the device a command, external to the POST routine, which directs the POST routine to thereafter separately execute each of the testing subroutines of the POST. If a run error occurs in any testing subroutine as it is being separately executed, a signal indicative of the run error and particular testing subroutine in which it occurred is sent to the system.

Abstract: To reliably maintain an EMI grounding connection between a sheet metal computer chassis wall and a computer cover wall that may be removably placed against the outer side of the chassis wall, a lance structure is formed in the chassis wall, and opposing installation notches are formed in the chassis wall on opposite sides of the lance opening. Transversely enlarged end portions of an elongated arcuate sheet metal grounding strip are inserted inwardly through the wall notches and captively retained within the lance structure with a longitudinally intermediate portion of the arcuate strip body extending outwardly through the chassis wall lance opening. When the cover wall is operatively installed on the chassis wall the grounding strip is resiliently flattened and compressed between the lance strip and the installed cover wall to maintain an EMI grounding path between the contiguous chassis and cover walls.

Abstract: A feedback system coupled between both outputs of a dual flyback converter for detecting which output is loaded and for switching between one of two feedback circuits for regulating the voltage of the loaded output. The detection circuit includes a balanced voltage divider coupled in series between the two opposite polarity outputs. The voltage divider preferably comprises balanced high impedance resistors to prevent substantial loading. The voltage of the junction between the two resistors shifts away from the loaded output because of an increase of the voltage level of the unloaded output caused by leakage inductance of the switching transformer. The detection circuit also includes a comparator, which detects the voltage shift and asserts its output to a switch circuit, which switches control between the two feedback circuits to control the loop and appropriately regulate the loaded output voltage. The switch circuit is preferably an analog switch including one or more field-effect transistors.

Abstract: A dual processor computer system is disclosed that includes a processor failure detection and recovery circuit which initially designates one of the processing units as the lead-off master and the other processing unit as a slave. The processor failure detection and recovery circuit includes a timer unit which begins the countdown of a predetermined period in response to the initial resetting of the master and slave processors. The processor failure and detection circuit further includes a control unit which determines whether the master processor fails to reset or suffers from a hard failure by determining whether a bit of a storage unit has been set in response to software code intended for execution by the master processor during initialization. If the bit is not set before the lapse of the predetermined time period following reset, the control unit changes the designation of the slave processor to master and simultaneously resets the re-designated master.

Abstract: Disclosed are an apparatus and method for coupling a heat sink to a heat-producing electronic component, such as a microprocessor, into an assembly.

Abstract: A computer cover structure is removably slid over an associated computer chassis to place facing end walls of the cover and chassis in a contiguous, parallel relationship, the end walls are automatically aligned with one another, in two perpendicular directions parallel to their facing side surfaces, by a plurality of outwardly projecting lance strips associated with the cover structure end wall and received by corresponding elongated, generally diamond-shaped openings formed in the chassis end wall. The wall openings are longer and wider than the outwardly projecting longitudinally intermediate portions of the lance strips, and have oppositely sloped facing side edges. Initially, the longitudinally intermediate lance strip portions freely enter their associated chassis wall openings.

Abstract: A docking detection and suspend circuit for portable computer/expansion chassis docking system. A first circuit within the portable computer is capable of detecting an impending electrical coupling of the portable computer to a corresponding docking station and generating a signal indicating the impending coupling. A second circuit within the portable computer and coupled to the first circuit is capable of receiving the signal and placing the portable computer in a suspend mode at least until the portable computer fully electrically couples to the docking station. The present invention relieves a computer user of the task of manually placing the portable computer in the suspend mode prior to docking with the docking station. The present invention protects components within both the portable computer and the docking station from being damaged by docking the portable computer when in a normal operational mode and prevents the user's data from being corrupted.

Abstract: A method and apparatus for performing cache snoop testing on personal computers using software to initiate DMA cycles. The computer system includes an extended capabilities parallel port (ECP), which includes a 16 bit first-in first-out buffer (FIFO) that can be accessed in a test mode where software can manually write and read the FIFO. This FIFO in the ECP parallel port is used according to the present invention to implement cache snoop testing diagnostics on personal computers. In the preferred embodiment, various hardware subsystems such as system memory, the ECP port, and the DMA controller are tested first to ensure that, if a failure occurs during cache testing, the system can differentiate between cache snoop failures and other subsystem failures. Cache snoop testing according to the present invention uses the capability provided by the ECP parallel port to generate DMA cycles which transfer data from the ECP FIFO buffer into the system memory via software.

Abstract: A system for controlling the rate and duration of battery charging. A microprocessor is connected in a battery current signal feedback loop and used to control the battery charge cycle. The rate of charge is gradually stepped up at the beginning of the charge cycle until the charging current reaches a defined maximum value, and thereafter maintained between the maximum and a defined minimum value for the duration of the charge cycle. The microcontroller terminates the charge cycle when the battery charging current begins to increase while the rate of charge remains constant, this being an indication that the battery is fully charged. Sensors input signals to the microcontroller to prevent or terminate charging if the battery cells are not within an appropriate temperature range, or if a short circuit or other adverse condition arises.

Abstract: In a computer system having a computer bus drive circuit capable of providing drive current to an individual line of a computer bus coupled thereto, a circuit for determining a proper level for the drive current and a method of making such determination. The circuit comprises: (1) a detection circuit, coupled to the individual line of the bus, for monitoring a response of the individual line of the bus to changes in state thereof during an operation of the computer system and providing an indication of the response and (2) a drive current establishment circuit, coupled between the detection circuit and the computer bus drive circuit, for establishing the proper level for the drive current in response to the indication produced by the detection circuit during an operation of the computer system.

Abstract: A specially designed metal grounding cap is placed over a metal-plated housing boss upon which a printed circuit board is to be mounted by extending a screw through a hole in the circuit board and tightening the screw into a metal insert previously forced into the free end of the mounting boss. As the screw is tightened into the boss insert, an EMI grounding pad on the underside of the circuit board engages an end wall of the grounding cap and pushes it into forcible engagement with the inner end of the boss. The forcible engagement of the grounding cap end wall causes leg portions of the cap to pivot inwardly and engage portions of the plated boss side wall between the boss insert and the metal plated housing wall from which the boss inwardly projects.

Abstract: Disclosed are a personal digital assistant ("PDA") and a method of providing data to the PDA. The PDA includes: (1) a chassis having first and second noncoplanar surfaces thereon and containing computer processing circuitry therein, (2) a visual display located on one of the first and second surfaces, the visual display coupled to the circuitry to allow the circuitry to drive the visual display and (3) a plurality of momentary keys located on both of the first and second surfaces and coupled to the circuitry, the plurality cooperating to form a chord keyboard to thereby allow multiple ones of the plurality to be depressed at a time to form a chord, the circuitry interpreting the chord as a single keystroke.

Abstract: An inbound telemetry device and method of operation thereof are provided in which the inbound telemetry device becomes activated should one or the other of two different events occur. The inbound telemetry device is located at a predetermined site and is coupled by a telephone line to a central host. When a real time clock within the device reaches a predetermined point in time, the device seizes the phone line and dials a predetermined telephone number and transmits collected data over the phone line to the central host or other station having a need for the information. The inbound telemetry device includes a ring counter which counts the number of rings in a particular call whether the call is from the central host or another telephone user.

Abstract: A outbound telemetry device type of meter interface unit (MIU) is provided which enables the automated collection of utility consumption information from a telephone subscriber's site via a conventional subscriber phone line between a central office and the subscriber's site. The unit includes a processor which is capable of collecting consumption information at the subscriber's site. The processor draws electrical power from the phone line in an electrically isolated fashion. When the unit detects the presence of an alerting signal intended for that particular unit, the unit seizes the phone line. The processor then transmits telemetry data with respect to the information back over the phone line. The unit continues the seizure of the phone line for so long as the telemetry data transmission from the processor continues. The unit includes a data detection circuit which detects when the telemetry data transmission ceases.

Abstract: A signal processing circuit is provided, one embodiment of which is employed in an inbound telemetry device such as an inbound MIU, another embodiment of which is employed in an outbound telemetry device such as an outbound MIU, for example. The inbound signal processing circuit monitors and senses conditions on a phone line coupled thereto to determine when the line is available or not available for use by the inbound telemetry device. More specifically, the processing circuit includes a sensing circuit which senses when other communications devices coupled to the phone line are off-hook and hence the line is not available. The processing circuit advantageously employs the same sensing circuit to determine when ringing signals are present on the line such that the line is not available.

Abstract: A data processing system includes a microprocessor operable in a burst mode to read data from a memory. The memory, its controller and bus are operable in a pipelining mode. Array logic is connected between the microprocessor and the remaining elements for converting the burst mode to the pipeline mode.

Abstract: A personal computer enclosure is provided which is reinforced by a disk drive support structure inside the box. The enclosure is a substantially parallelepiped outer box having an opening for providing access to the interior of the box. The box includes a plurality of mounting locations on the interior of the box. The inner support structure includes a plurality of bays for receiving respective disk drives therein. These bays communicate with the opening in the enclosure. The structure is attached to said outer box at said mounting locations to provide structural integrity thereto.

Abstract: A microprocessor based computer system is provided which includes a reset circuit having a phase error detector for detecting a phase error between an initial reset signal and a clock signal provided to the microprocessor clock input. The reset circuit further includes a phase error corrector for adjusting the phase of the clock signal if a phase error is detected so as to substantially minimize the phase error. The reset circuit includes a reset signal regenerator for providing a new reset signal to the reset input of the microprocessor when the phase of the clock signal is adjusted.