Abstract: A user can easily identify the content of data (the value or the state of the data), such as a credit balance, stored in a contactless IC module provided in a wrist-watch device having a communication function. A timepiece control unit 14 of a timepiece module 10 transmits a confirmation command for the data, such as the credit balance, to a contactless IC module 60 every determination cycle period TSP, and receives the data stored in the contactless IC module 60. When the value of the stored data (for example, the amount of balance) becomes smaller than a predetermined value, the timepiece control unit 14 causes a second hand to perform an irregular movement noticeably different from the regular timing movement. Accordingly, the user is able to easily identify the data content (for example, insufficient balance).

Abstract: A method for creating an ink-trail and implementing a partial ink layer in a pen based computing apparatus is described. The partial ink layer, which is smaller than a display window of a computing apparatus, is located at a starting address with a shape and size that fits within the display widow. An ink trail is created within the ink layer that simulates ink flowing from the pen to paper while a character, or several cursive characters, is formed by the pen while touching a touch screen overlaying the display screen of the computing apparatus. The ink trail is erased when the pen is removed from the touch screen. The bit depth of the pixels in the partial ink layer are less than for the pixels of the main display and can be as few as 2, which includes a transparency bit.

Abstract: The invention is directed to a method and apparatus for selectively reducing the depth of digital data. Multiple bit digital data is transmitted to a data receiving device on a plurality of data output lines. Each data output line corresponds, respectively, to a unique one of the bits of the data. A determination is made whether, in the data receiving device, a power saving mode of operation of the device is to be initiated. If so, one or more of the data output lines are selected as non-transmitting data lines, one or more remaining data input lines are driven with corresponding bits of the data, and the non-receiving data lines are placed in a neutral state.

Abstract: An information processing system that is configured in such a manner that computational processing is performed on input data in accordance with a processing sequence, for outputting data, comprises: a plurality of arithmetic units (7-1 to 7-x), each computing at an arithmetic precision 2m bits (where m is a natural number) based on the processing sequence; and a plurality of cascade connection terminals for cascading these arithmetic units each other. When the maximum arithmetic precision that is required during computational processing is 2n bits (where n is a natural number and is fixed), x numbers of (where x is a natural number) the arithmetic units are cascaded in a manner such that the inequality x?2n/2m is satisfied. When an arithmetic precision of 2n1 bits (where n1?n, and n1 is variable) is necessary during computational processing, x1 numbers of the arithmetic units are cascaded in a manner such that the inequality x1?2n1/2m (where x1 is a natural number and is variable) is satisfied.

Abstract: A graphics controller includes a memory region configured to store image data for display on a display panel in communication with the graphics controller. Interface circuitry modules where each of the interface circuitry modules is configured to transmit data from the graphics controller over a set of shared data lines are provided. Selection circuitry configured to select data from one of the interface circuitry modules for transmission over the set of shared data lines is included. Line sharing circuitry configured to inform each of the interface circuitry modules to transmit control data is included. The line sharing circuitry is further configured to generate select signals for the selection circuitry. The select signals enable the selection circuitry to select the data from one of the interface circuitry modules for transmission over the shared data lines. A method for driving a display panel and peripheral devices associated with the display panel through common data lines is also provided.

Abstract: A piezoelectric actuator A has an oscillator 10 that has a flat base layer 32 and piezoelectric elements 30, 31 layered on the base layer 32 and oscillates as a result of a drive signal applied to the piezoelectric elements 30, 31, and a rotor 100 driven by vibrations from the oscillator 10. The piezoelectric actuator A includes a fastening part 11 for securing the oscillator 10, and lead substrates 14A, 14B that are secured to the fastening part 11 for applying a drive signal to the piezoelectric elements from a drive circuit 500 for driving the piezoelectric elements 30, 31. The lead substrates 14A, 14B have connecting parts 17A–17C extending to the power supply electrodes 33A, 33C and a detection electrode 34.

Abstract: When a time keeping apparatus is in a power saving mode, performing time display is stopped, and the apparatus periodically receives a time data from outside and sets the data to a second time counter 98 and an hour-and-minute time counter 99. When the operation mode of the time keeping apparatus is switched from the power saving mode to the display mode, the apparatus resumes to display the current time based on the counted values in the second time counter 98 and the hour and minute time counter 99.

Abstract: A graphics display controller providing enhanced read/write efficiency for interfacing with a RAM-integrated graphics display device. According to the invention, a graphics display controller is disclosed for interfacing between a host and a graphics display device having an associated memory is provided that includes an embedded memory, a format converter, and a data storage memory. The embedded memory is adapted for storing frames of video data received from a host. The format converter is adapted to convert the video data in at least one of two ways: (1) from the data format of the host to the data format of the display device and (2) from the data format of the display device to the data format of the host. The data storage memory has a memory size that is smaller than the embedded memory, and defines a data path that bypasses the embedded memory but connects to the format converter.

Abstract: A multiplex driving method is provided for a liquid crystal cell device having a liquid crystal layer disposed between a pair of substrates, a plurality of row electrodes arranged on one of the substrates and a plurality of column electrodes arranged on the other substrate. The method comprises the steps of sequentially selecting a group of the plurality of row electrodes during a selection period, simultaneously selecting the row electrodes comprising the group, and dividing and separating the selection period into a plurality of intervals within one frame period.

Abstract: A document reading apparatus reduces processing time and affords excellent ease of use when reading a slip document to acquire both magnetically read data and image data. Transportation unit 19, 20 convey slips through a transportation path. Magnetic reading unit 21, 22 output magnetically read data acquired by reading the printed magnetic ink characters from the slip as the slip passes through the transportation path, and optical reading unit 23, 24 output image data captured by optically imaging the same slip during the same pass through the transportation path. A control unit 11 interprets control commands and controls slip transportation, the magnetic reading process, and the optical reading process accordingly. A single-pass multiple-reading command controls executing a single-pass multiple-reading process for applying both the magnetic reading and optical reading of specified slip during a single pass through the transportation path.

Abstract: In a label printer in which either a peeling mode or non-peeling mode can be selected as the label dispensing mode, labels are printed and thus wasted when the operator loads the label paper into a transportation path that does not match the desired dispensing mode. This problem is solved by a label printer enabling selecting as the printing configuration either a peeling configuration for peeling printed labels from the web of label paper 11, or a non-peeling configuration in which the printed labels are not separated from the web of the label paper 11. A printing configuration selection unit 27 enables selecting which printing configuration to use. To operate in the non-peeling mode, the label paper 11 is loaded into a first paper transportation path A. To operate in the peeling mode, the label paper 11 is loaded to a second paper transportation path B. A cover unit 2 can be opened and closed to enable handling the label paper, and takes the label printer off-line when the cover unit 2 is opened.

Abstract: A central processing unit (CPU) configured to apply an intelligent wait methodology is provided. The CPU includes a chip select module that defines a chip select signal associated with an external device. The chip select module includes an address space configured to store addresses associated with the external device. The address space provides an address section. The address section is associated with the external device and is subdivided into address sub-sections associated with an address range and assigned through the chip select signal. The address sub-sections are configured to determine a bus cycle based on an association with either the CPU monitoring a wait line between the CPU and the external device or the CPU waiting for a number of wait states. A device and a method for optimizing a bus cycle length between a CPU and an external device in communication with the CPU are provided.

Abstract: A graphics controller providing flexible access to a graphics display device by a host. The controller includes an input bus for coupling to an output bus of the host, an output bus for coupling to the input bus of the graphics display device, a video processing circuit having an input coupled to the input bus of the graphics controller and an output coupled to the output bus of the graphics controller, and a bypass switching circuit adapted to switchably couple the input bus of the graphics controller to the output bus of the graphics controller so as to bypass the video processing circuit.

Abstract: By using a CR oscillating circuit and a PLL oscillating circuit selectively, these two oscillating circuits are used as a high frequency, low power consumption, short waiting time for stable oscillation, and low operating voltage oscillating circuit.

Abstract: A method for debugging including the steps of receiving code having a software breakpoint function therein, running the code for the purpose of debugging, monitoring the code to detect the presence of the software breakpoint function, recognizing the software breakpoint function, determining an action to be performed based on the software breakpoint function, and implementing the action. The present invention also includes an apparatus for implementing the method for debugging and a medium embodying a program of instructions for execution by a device to perform the method for debugging.

Abstract: An interface between a host and a slave device having a latency greater than the latency of the host is disclosed. The interface includes a register and a state machine. The state machine provides data to the host from any address in the slave in two host read cycles. The state machine receives a first request from the host for data stored at a first address in the slave at a first time. The state machine stores the data returned from the slave in response to the first request in the register at a second time. The state machine receives a second request from the host for data stored at a second address in the slave at a third time. The state machine provides the data specified in the first request to the host at a fourth time. The state machine is additionally adapted to provide data to the host from a second address in the slave in one read cycle.

Abstract: A system and method for continuously tracing transfer rectangles for performing image data transfers includes a display controller with control logic, a rectangle module, and a coordinates module. The rectangle module detects write operations to on-screen data in a video memory, and then updates a primary transfer rectangle during a normal mode to include pixel data from the foregoing write operations. The coordinates module stores the primary transfer rectangle for performing a current transfer operation. The coordinates module enters a pause mode before initiating the current transfer operation, and retains the primary transfer rectangle during the pause mode. The coordinate module also stores a secondary transfer rectangle formed during the pause mode by detecting the foregoing write operations. The controller logic instructs the coordinates module to resume the normal mode after the current transfer operation concludes.

Abstract: A drive circuit is provided that can drive a display panel with low power consumption, and an electro optical device including the drive circuit and its drive method are included. Switching signals RSEL, GSEL, and BSEL for demultiplexing are produced so as to control turning switching elements DSWR, DSWG, and DSWB for demultiplexing on and off, which separate data signal where R, G, and B are multiplexed and transmitted. An overlapped period, for periods of activating RSEL, GSEL, and BSEL is set between the timing of changing polarity of common voltage and the timing of assuring writing data signal to a pixel electrode. A drive circuit includes a reference voltage production circuit and a digital to analog conversion circuit and an output circuit, which outputs a programmed voltage (a reference voltage having the same phase as the common voltage) during the overlapped period.

Abstract: A time measurement system includes a master timepiece and a slave timepiece 3. The master timepiece includes a time signal generating circuit that receives a standard frequency and time signal and generates a time signal being receivable by a motor driving coil 35 of the slave timepiece 3; and a transmitter circuit and a coil that transmit this signal. The slave timepiece 3 includes a time counter 33 that keeps time on the basis of a reference signal; a driving motor with the driving coil 35; a receiver circuit 37 that receives the time signal using the driving coil 35; a control circuit 38 that corrects the time counter 33 on the basis of the received time signal; and a time display unit 36 that displays time. Since the driving coil 35 is used, increases in the number of components and cost are suppressed. The time can be adjusted within a short period of time. Waterproof abilities are improved.

Abstract: Signal management control units 471-47n of respective scan drivers LSI in an LCD module are cascade-connected and each have the same construction. A detected signal of the signal management control unit 47J is a data signal latch clock LP applied to a terminal CKB1. A detected signal of the signal management control unit 472 is a frame start signal SP applied to a terminal CKB2. A detected signal of the signal management control unit 47n is an AC-transforming clock FR applied to a terminal CKBn. The signal management control unit 471 includes a signal stop detection circuit 48 serving as a signal detection means for detecting a stop of the detected signal and a sequence processing circuit 51 consisting of a signal delay circuit 49 and a logic circuit 50. When stopping oscillations of, e. g., the frame start signal SP, outputs T1-Tn of the circuit 51 change to an L level. Hence, a display-off signal DF of the LCD module assumes the L level. A liquid crystal panel is forcibly set in a display-off mode.