Abstract: A metal optical grayscale mask includes a layer of metal film which is deposited on transparent substrate, and different transparency pattern which is formed by laser writing on the surface of the metal film. The pattern is continuous, in type of array or random pattern. The grayscale is within 3.0 OD-0.05 OD. The thickness of the metal film is 5-100 nm. A manufacturing method of the metal optical grayscale mask includes that the selected transparent substrate is rinsed by the general semiconductor rinse process, the metal film is deposited on the transparent substrate then different transparency pattern is formed by laser writing on the surface of the metal film. The pattern is continuous, in type of array or the random pattern. The grayscale mask is low in price, antistatic electricity performance is good, the resolution can surpass optical diffraction limit. The manufacturing method is simple.

Abstract: A semiconductor device includes a substrate portion having a plurality of diffusion regions defined therein. A gate electrode level region is formed above the substrate portion to include conductive features defined to extend in only a first parallel direction. Adjacent ones of the conductive features that share a common line of extent are fabricated from respective originating layout features separated from each other by an end-to-end spacing of substantially equal and minimum size across the gate electrode level region. A width of the conductive features within a 5 wavelength photolithographic interaction radius is less than a 193 nanometer wavelength of light used in a photolithography process for their fabrication. Some conductive features extend over the plurality of diffusion regions to form PMOS or NMOS transistor devices. A total number of the PMOS and NMOS transistor devices in the gate electrode level region is greater than or equal to eight.

Abstract: A layout of a cell of a semiconductor device is disclosed to include a diffusion level layout including a plurality of diffusion region layout shapes, including a p-type and an n-type diffusion region separated by a central inactive region. The layout of the cell includes a gate electrode level layout corresponding to an entire gate level of the cell. The gate electrode layout includes a number of linear-shaped layout features placed to extend in only a first parallel direction. Each of the number of the linear-shaped layout features within the gate electrode level layout of the restricted layout region is rectangular-shaped. Linear-shaped layout features within the gate electrode level layout extend over one or more of the p-type and/or n-type diffusion regions to form PMOS and NMOS transistor devices. A total number of the PMOS and NMOS transistor devices in the cell is greater than or equal to eight.

Abstract: A semiconductor device includes a substrate portion including a plurality of diffusion regions defined in a non-symmetrical manner relative to a virtual bisecting line. A gate electrode level region above the substrate portion includes a number of conductive features that extend in only a first parallel direction. Adjacent conductive features that share a common line of extent in the first parallel direction are fabricated from respective originating layout features separated by an equal and minimal sized end-to-end spacing. Conductive features are defined along at least four different virtual lines of extent in the first parallel direction. A width of the conductive features within a photolithographic interaction radius is less than a wavelength of light of 193 nanometers as used in a photolithography process for their fabrication. The photolithographic interaction radius is five times the wavelength of light used in the photolithography process.

Abstract: A first signal processing circuit performs predetermined signal processing on a first signal to provide a change to a characteristic value thereof, and then outputs a second signal. A second signal processing circuit performs predetermined signal processing on the second signal to provide a change to a characteristic value thereof, and then outputs a third signal. A first and a second switching power supplies respectively supply power supply voltages to the first and second signal processing circuits. An amount of change provided to the characteristic value of the first signal by the first signal processing circuit, and an amount of change provided to the characteristic value of the second signal by the second signal processing circuit, are dependent on the respective power supply voltages.

Abstract: A layout of a cell of a semiconductor device is disclosed to include a diffusion level layout including a plurality of diffusion region layout shapes, including p-type and n-type diffusion regions. The layout of the cell also includes a gate electrode level layout defined to include a number of linear-shaped layout features placed to extend in only a first parallel direction. Each of the number of the linear-shaped layout features within the gate electrode level layout of the restricted layout region is rectangular-shaped. Linear-shaped layout features within the gate electrode level layout extend over one or more of the p-type and/or n-type diffusion regions to form PMOS and NMOS transistor devices. A total number of the PMOS and NMOS transistor devices in the cell is greater than or equal to eight.

Abstract: An apparatus, system and method for cleaning a substrate edge include a bristle brush unit that cleans bevel polymers deposited on substrate edges using frictional contact in the presence of cleaning chemistry. The bristle brush unit is made up of a plurality of outwardly extending vanes and is mounted on a rotating shaft. An abrasive material is distributed throughout and within the outwardly extending vanes of the bristle brush unit to provide the frictional contact. The bristle brush unit cleans the edge of the substrate by allowing frictional contact of the plurality of abrasive particles with the edge of the substrate in the presence of fluids, such as cleaning chemistry, to cut, rip and tear the bevel polymer from the edge of the substrate.

Abstract: A semiconductor device includes a substrate portion having a plurality of diffusion regions defined therein in a non-symmetrical manner relative to a virtual line defined to bisect the substrate portion. The semiconductor device includes a gate electrode level region including a number of conductive features defined to extend in only a first parallel direction. Adjacent ones of the conductive features that share a common line of extent in the first parallel direction are fabricated from respective originating layout features separated by an end-to-end spacing having a size that is substantially equal across the gate electrode level region and is minimized to an extent allowed by a semiconductor device manufacturing capability. Conductive features are defined along at least four different virtual lines of extent in the first parallel direction. A width of the conductive features is less than a wavelength of light used in a photolithography process for their fabrication.

Abstract: A cell of a semiconductor device is disclosed to include a diffusion level including a plurality of diffusion regions separated by inactive regions. The cell also includes a gate electrode level including a number of conductive features defined to extend in only a first parallel direction. Adjacent ones of the number of conductive features that share a common line of extent in the first parallel direction are fabricated from respective originating layout features that are separated from each other by an end-to-end spacing having a size that is substantially equal across the gate electrode level region and is minimized to an extent allowed by a semiconductor device manufacturing capability. The gate electrode level includes conductive features defined along at least four different virtual lines of extent in the first parallel direction. The cell also includes a number of interconnect levels formed above the gate electrode level.

Abstract: A cell of a semiconductor device is disclosed to include a diffusion level including a plurality of diffusion regions separated by inactive regions. The cell also includes a gate electrode level including a number of conductive features defined to extend in only a first parallel direction. Each of the conductive features within the gate electrode level is fabricated from a respective originating rectangular-shaped layout feature. The gate electrode level includes conductive features defined along at least four different virtual lines of extent in the first parallel direction. The cell also includes a number of interconnect levels formed above the gate electrode level.

Abstract: A semiconductor device includes a substrate portion having a plurality of diffusion regions defined therein in a non-symmetrical manner relative to a virtual line defined to bisect the substrate portion. The semiconductor device includes a gate electrode level region including a number of conductive features defined to extend in only a first parallel direction. Adjacent ones of the number of conductive features that share a common line of extent in the first parallel direction are fabricated from respective originating layout features that are separated from each other by an end-to-end spacing having a size that is substantially equal across the gate electrode level region and is minimized to an extent allowed by a semiconductor device manufacturing capability. The gate electrode level region includes conductive features defined along at least four different virtual lines of extent in the first parallel direction.

Abstract: A cell of a semiconductor device is disclosed to include a diffusion level including a plurality of diffusion regions separated by inactive regions. The cell also includes a gate electrode level including conductive features defined to extend in only a first parallel direction. Adjacent ones of the conductive features that share a common line of extent in the first parallel direction are fabricated from respective originating layout features that are separated from each other by an end-to-end spacing having a size that is substantially equal across the gate electrode level region and is minimized to an extent allowed by a semiconductor device manufacturing capability. The gate electrode level includes conductive features defined along at least four different virtual lines of extent in the first parallel direction. A width of the conductive features is less than a wavelength of light used in a photolithography process for their fabrication.

Abstract: Methods, and associated devices, media, and systems, for establishing a communication link between a host system and a storage device are provided. One method includes an operation for providing on the host a communication stack including a Transmission Control Protocol/Internet Protocol (TCP/IP) module and a host physical layer module. The storage device includes a storage command extractor, and the method includes another operation for establishing a communication channel between an application in the host and the storage device, where the communication channel uses the communication stack and the storage command extractor. In the method, the TCP/IP module converts TCP/IP commands received from the application in the host to storage commands for the storage device.

Abstract: A cell of a semiconductor device includes a diffusion level including a plurality of diffusion regions separated by inactive regions. The cell also includes a gate electrode level including conductive features defined to extend in only a first parallel direction. Adjacent ones of the conductive features that share a common line of extent in the first parallel direction are fabricated from respective originating layout features that are separated from each other by an end-to-end spacing having a size that is substantially equal and minimized across the gate electrode level. Some of the conductive features form respective PMOS and/or NMOS transistor devices. A total number of the PMOS and NMOS transistor devices in the cell is greater than or equal to eight. A width of the conductive features in the gate electrode level is less than a wavelength of light used in a photolithography process for their fabrication.

Abstract: An approach is provided in embodiments of the present invention for utilizing Java™ Management Extensions (JMX) as a back end to “instrument” (i.e. monitor and control) computer system resources, including servers, devices, and applications etc., within standard resource management model(s) that are external to Java™. For example, JMX can be used as a back end to instrument WS-Management resources—in particular, JMX MBeans can be used to implement Common Information Model (CIM) WS-Management resources.

Abstract: A layout of a cell of a semiconductor device is disclosed to include a diffusion level layout including a plurality of diffusion region layout shapes, including p-type and n-type diffusion regions. The layout of the cell also includes a gate electrode level layout is defined to include a number of linear-shaped layout features placed to extend in only a first parallel direction. Each of the number of the linear-shaped layout features within the gate electrode level layout of the restricted layout region is rectangular-shaped. Linear-shaped layout features within the gate electrode level layout extend over one or more of the p-type and/or n-type diffusion regions to form PMOS and NMOS transistor devices. A number of the PMOS transistor devices is equal to a number of the NMOS transistor devices in the cell.

Abstract: Methods and apparatus for a gate-length biasing methodology for optimizing integrated digital circuits are described. The gate-length biasing methodology replaces a nominal gate-length of a transistor with a biased gate-length, where the biased gate-length includes a bias length that is small compared to the nominal gate-length. In an exemplary embodiment, the bias length is less than 10% of the nominal gate-length.

Abstract: Computer implemented methods for conducting interactive surveys that define aspects of a web page, is disclosed. One method includes generating an interactive survey user interface (UI), where the interactive survey UI provides a plurality of selectable nomenclature items for a plurality of page objects of the web page. Then, enabling selection of one nomenclature item from the plurality of selectable nomenclature items. A drag and drop operation enables the selection of the one nomenclature item and dragging to the one of the plurality of page objects to define a placement for the one nomenclature item. The selection of the one nomenclature item and the defined placement is received to build metrics from multiple survey participants, where the metrics are used to define recommendation for rendering the plurality of page objects on the web page. The recommendations identify nomenclature and placement of page objects for the design of the web page.

Abstract: Methods for optimizing webpage content by micro-bucket testing user customization to the webpage include presenting a plurality of modules at a webpage based on a request from a user. The modules define an intent of the webpage. A change defining customization to one or more modules within the webpage is detected. A test case representing the change is automatically generated. The generated test case is a modified webpage having the customization. The webpage is presented to a first segment of users as a control page and the modified webpage is presented to a second segment of users in response to a request for the webpage. User interaction by the first and segment of users is monitored at the webpage and the modified webpage to determine website metrics of the corresponding webpages. The website metrics is used in defining a new control page of the webpage from the modified webpage or retaining the webpage as the control page.

Abstract: A method for prioritized erasure of a non-volatile storage device, the method including the steps of: providing at least one flash unit of the storage device, wherein each flash unit has a plurality of blocks; writing data into the plurality of blocks; assigning an erasure-priority to each block, wherein the erasure-priority correlates with an erasure-priority of the data; and erasing the data in each block according to the erasure-priority of each block upon receiving an emergency-erase command. Preferably, the step of writing data into the plurality of blocks is performed in an arbitrary order in a first flash unit, and the step of writing into subsequent flash units is performed in correlation with the order in the first flash unit. Preferably, the step of erasing includes aborting erasure, before completing the erasure, for at least some of the plurality of blocks.