Abstract: The embodiments of the present invention provide methods for cleaning patterned substrates with fine features. The methods for cleaning patterned substrate have advantages in cleaning patterned substrates with fine features without substantially damaging the features by using the cleaning materials described. The cleaning materials are fluid, either in liquid phase, or in liquid/gas phase, and deform around device features; therefore, the cleaning materials do not substantially damage the device features or reduce damage all together. The cleaning materials containing polymers of a polymeric compound with large molecular weight capture the contaminants on the substrate. In addition, the cleaning materials entrap the contaminants and do not return the contaminants to the substrate surface. The polymers of one or more polymeric compounds with large molecular weight form long polymer chains, which can also be cross-linked to form a network (or polymeric network).

Abstract: The embodiments of the present invention provide improved materials for cleaning patterned substrates with fine features. The cleaning materials have advantages in cleaning patterned substrates with fine features without substantially damaging the features. The cleaning materials are fluid, either in liquid phase, or in liquid/gas phase, and deform around device features; therefore, the cleaning materials do not substantially damage the device features or reduce damage all together. To assist removing of particles from the wafer (or substrate) surfaces, the polymeric compound of the polymers can contain a polar functional group, which can establish polar-polar molecular interaction and hydrogen bonds with hydrolyzed particles on the wafer surface. The polymers of a polymeric compound(s) with a large molecular weight form long polymer chains and network.

Abstract: Regular layout shapes are placed in accordance with a virtual grate. A determination is made as to whether an unoccupied layout space adjacent to a regular layout shape to be reinforced, and extending in a direction perpendicular to the regular layout shape, is large enough to support placement of a sub-resolution shape. Upon determining that the unoccupied layout space is large enough to support placement of the sub-resolution shape, the sub-resolution shape is placed so as to be substantially centered upon a virtual line of the virtual grate within the unoccupied layout space. Also, one or more sub-resolution shapes are placed between and parallel with neighboring regular layout shapes when windows of lithographic reinforcement associated with each of the neighboring regular layout shapes permit. The sub-resolution shapes may be placed according to a virtual grate, or may be placed based on proximity to edges of the neighboring regular layout shapes.

Abstract: Methods for plating substrates are herein defined. One method includes providing a plating assembly having a plating source in a plating fluid and a plating facilitator in the plating fluid, and defining a plating meniscus between the plating source and the plating facilitator. The plating meniscus being contained in a path of the plating assembly. The method further includes traversing a substrate through the path of the plating assembly. The substrate being charged so that plating ions are attracted to a surface of the substrate when the plating meniscus is present on the surface of the substrate, wherein the substrate traversing through the path of the plating assembly enables plating across the surface of the substrate. And, inducing a uniform charge in the path where the plating meniscus is formed, such that charge from the plating source is substantially uniformly directed toward the plating facilitator as the substrate that is charged moves through the path of the plating assembly.

Abstract: First and second virtual grates are defined as respective sets of parallel virtual lines extending across a layout area in first and second perpendicular directions, respectively. The virtual lines of the first and second virtual grates correspond to placement locations for layout features in lower and higher chip levels, respectively. Each intersection point between virtual lines of the first and second virtual grates is a gridpoint within a vertical connection placement grid. Vertical connection structures are placed at a number of gridpoints within the vertical connection placement grid so as to provide electrical connectivity between layout features in the lower and higher chip levels. The vertical connection structures are placed so as to minimize a number of different spacing sizes between neighboring vertical connection structures across the vertical connection placement grid, while simultaneously minimizing to an extent possible layout area size.

Abstract: Input devices for interfacing with a game console to interact with a computer program are disclosed. In one example, the input device includes a controller with a handle and a spherical object that is connected to a first end of the handle. The controller further includes a circuit that identifies the position of the handle. The circuit further includes communication logic to communicate the identified position to the game console during interaction with the computer program. The controller further includes control inputs connected to a second end of the handle, wherein the spherical object is placed in contact with a surface when held by the handle and the circuit updates the identified position of the handle as the handle is pivoted on the surface. The control inputs providing commands that are exchanged with the game console to further interact with the computer program.

Abstract: Provided is a method and an apparatus for maintaining state information between a stateless environment and a stateful environment. Specifically, a front-end process operates a stateless environment, such as providing web services via the HyperText Transfer Protocol. Because HTTP is inherently stateless, a back-end process operates a stateful environment by managing multiple modules. Some of the modules can be login modules that request login information for an authentication process. The authentication process can be the Java Authentication and Authorization Service (JAAS). The back-end process accumulates state information and transmits the state information to the front-end process when modules request further information. By managing the authentication process from the back-end process, the stateful environment is established for the stateless environment.

Abstract: A cell of a semiconductor device is disclosed to include a diffusion level including a plurality of diffusion regions separated by inactive regions. The cell also includes a gate electrode level including a number of conductive features defined to extend in only a first parallel direction. Each of the conductive features within the gate electrode level is fabricated from a respective originating rectangular-shaped layout feature. The gate electrode level includes conductive features defined along at least four different virtual lines of extent in the first parallel direction. A width of the conductive features within the gate electrode level is measured perpendicular to the first parallel direction and is less than a wavelength of light used in a photolithography process to fabricate the conductive features. The cell also includes a number of interconnect levels formed above the gate electrode level.

Abstract: A variable delay circuit delays a carrier signal having a predetermined frequency, and outputs a modulated signal. A delay setting unit sets a delay period for the variable delay circuit according to a data signal to be modulated. The delay setting unit assigns each symbol in the data signal to any one of positive edges and negative edges in the carrier signal, and sets a delay period for the variable delay circuit at the timing at which a positive edge in the carrier signal passes through the variable delay circuit, according to the symbol value in the data signal assigned to the positive edge. Furthermore, the delay setting unit sets a delay period for the variable delay circuit at the timing at which a negative edge in the carrier signal passes through the variable delay circuit, according to the symbol value in the data signal assigned to the negative edge.

Abstract: A plasma technique in which a plasma generation technique frequently used in various fields including a semiconductor manufacturing process is used, and generation of plasma instability (high-speed impedance change of a plasma) can efficiently be suppressed and controlled in order to manufacture stable products. In a method of disposing an object in a chamber and generating the plasma to treat the object, the chamber is sealed by a surrounding member so as to have an inner space, with at least a part of the member including a dielectric material, an RF induction coil is disposed outside the dielectric member, and a direct-current electric field is supplied into the inner space by a method of passing a direct current through the RF induction coil or another method, so that the plasma is stabilized.

Abstract: A method for cleaning a processing chamber that includes heating an inner surface of the processing chamber to a first temperature. The first temperature can be sufficient to cause a first species to become volatile. The first species can be one of several species deposited on the inner surface. A cleaning chemistry is injected into the processing chamber. The cleaning chemistry can be reactive with a second one of the species to convert the second species to the first species. The volatilized first species can also be output from the processing chamber. A system for cleaning the process chamber is also described.

Abstract: The Apparatuses, Methods, and Systems For Game Mechanics For Gifting (“GGM”) transform social graph, interactions, behavior and characteristics data inputs via various GGM components to create optimal gift-giving dynamics. In one embodiment, the GGM may receive a request to provide a gaming resource to a user. In response to the request, the GGM may aggregate and analyze interaction data to identify a provider with prior interactions with the user. The GGM may in turn request the provider for a gaming resource. The GGM may receive an indication to provide a gaming resource to the user in response to the request and may facilitate providing of a gaming resource to the user. The GGM may identify this indication as an instance of interaction and may update the user interaction data accordingly.

Abstract: A method and apparatus for managing a peer of a peer-to-peer network to search for an available resource includes organizing peers of the peer-to-peer network in a hierarchical structure based upon locality of the peers. A request for the available resource is received at a parent from a peer as a request bit string. An aggregate availability bit string representing an aggregate of resources available at all children associated with the parent is accessed to determine if one or more children of the parent are able to fulfill the resource request. The determination is by performing a logical operation with bits of the request bit string and bits of aggregate availability bit string. When more than one child of the parent is able to provide the requested resource, a child with available resource that is closest to the peer requesting the resource is identified. The available resource of the identified child is used to satisfy the resource request of the peer.

Abstract: The APPARATUSES, METHODS AND SYSTEMS FOR A MULTI-LEVEL IN-GAME CURRENCY PLATFORM (“MIC”) transform user transaction request input via various MIC components into transaction result output. In one embodiment, a request to calculate a dynamic conversion rate between a payment currency type and a requested virtual currency type for a user may be received. The base conversion rate between the payment currency type and the requested virtual currency type may be retrieved. A user characteristic indicative of the user's progress through a game that affects the base conversion rate may be determined, and a game progression adjustment to the base conversion rate due to the determined user characteristic may be calculated. The dynamic conversion rate may be calculated by adjusting the base conversion rate with the game progression adjustment and returned.

Abstract: The embodiments of the present invention provide improved materials for cleaning patterned substrates with fine features. The cleaning materials have advantages in cleaning patterned substrates with fine features without substantially damaging the features. The cleaning materials are fluid, either in liquid phase, or in liquid/gas phase, and deform around device features; therefore, the cleaning materials do not substantially damage the device features or reduce damage all together. The cleaning materials containing polymers of a polymeric compound with large molecular weight capture the contaminants on the substrate. In addition, the cleaning materials entrap the contaminants and do not return the contaminants to the substrate surface. The polymers of one or more polymeric compounds with large molecular weight form long polymer chains, which can also be cross-linked to form a network (or polymeric network).

Abstract: An integrated circuit (IC) die includes two bonding pads, that share a common logical function, such as signal input or signal output, separated by the width of the die, and preferably on opposite sides of the die. System-in-package devices are produced by steps including directly electrically connecting one or the other bonding pad to bonding pads of other, functionally different IC dies, with the bonding pads of the other IC dies, to which are connected bonding pads of common logical function of the IC dies of the present invention, being functionally identical but geometrically different. Multchip package devices are produced by stacking the IC dies of the present invention with other IC dies and directly electrically connecting one or the other bonding pad to different bonding pads of the other IC dies.

Abstract: A printing device comprising: a data acquiring unit configured to acquire image data; an image processing unit configured to generate display image data and printing image data based on the image data by with pixel value of a pixel at a first position in an image of the printing image data, performing an image process of modifying a pixel value of a first subject pixel of the printing image data at the first position or another position, the first position being determined according to a first parameter P1, with pixel value of a pixel at a second position in an image of the display image data, performing an image process of modifying a pixel value of a second subject pixel of the display image data at the second position or another position, the second position being determined according to a second parameter P2, and determining the second parameter P2 such that a ratio (P2/P1) of the second parameter P2 and the first parameter P1 is in a specified range that includes a ratio (Px2/Px1) of a display pixel coun

Abstract: A semiconductor chip is defined to include a logic block area having a first chip level in which layout features are placed according to a first virtual grate, and a second chip level in which layout features are placed according to a second virtual grate. A rational spatial relationship exists between the first and second virtual grates. A number of cells are placed within the logic block area. Each of the number of cells is defined according to an appropriate one of a number of cell phases. The appropriate one of the number of cell phases causes layout features in the first and second chip levels of a given placed cell to be aligned with the first and second virtual grates as positioned within the given placed cell.

Abstract: The invention provides a printing method of printing on a printing medium. The method includes: generating dot data that represents state of dot formation at each print pixel of a print image to be formed on the printing medium by performing a halftone process on image data that represents an input tone value of each pixel making up an original image; and generating the print image by forming dots on each of the print pixels according to the dot data. The halftone process determines the state of dot formation by using a dither matrix that stores a plurality of threshold values, the plurality of threshold values being used for determining state of dot formation at each of print pixels of the print image to be formed on the printing medium according to an input tone value.

Abstract: A layout of a cell of a semiconductor device is disclosed to include a diffusion level layout including a plurality of diffusion region layout shapes. The layout of the cell also includes a gate electrode level layout is defined to include a number of linear-shaped layout features placed to extend in only a first parallel direction. Each of the number of the linear-shaped layout features within the gate electrode level layout of the restricted layout region is rectangular-shaped. The gate electrode level layout includes linear-shaped layout features defined along at least four different lines of extent in the first parallel direction. The layout of the cell also includes a number of interconnect level layouts each of which is defined to pattern conductive features within corresponding interconnect levels above the gate electrode level.