Abstract: An equalization circuitry that includes a digital-to-analog converter having a voltage divider and a multiplexer coupled to the voltage divider is described. In one implementation, the digital-to-analog converter provides a control signal to a plurality of single-stage equalizer control logic circuits. Also, in one implementation, the multiplexer receives a plurality of inputs from the voltage divider and selects an output from the plurality of inputs. Furthermore, in one implementation, the voltage divider includes a plurality of resistors coupled in series. Also, in one implementation, the voltage divider further includes a first resistor coupled to the plurality of resistors, ground, and a lowest voltage input terminal of the multiplexer, where a voltage across the first resistor is an input voltage to the lowest voltage input terminal.

Abstract: Structures and methods to facilitate channel bundling are disclosed. In one embodiment, signal distribution circuitry includes a data path with at least two registers coupled to adjacent sets of data channels in a bundle of data channel sets. In another embodiment, self-switch circuits allow channels in a bundle of channel-sets to switch from bundle-wide signals to locally generated signals after the bundle-wide signals have been synchronously distributed to all channel sets in the bundle. In a particular embodiment, signal distribution circuitry is used to distribute a divided clock signal. In another particular embodiment, signal distribution circuitry is used to distribute enable signals for first-in first-out circuits (“FIFOs”) located in channels of each data channel set in a channel set bundle. In a particular aspect of an embodiment, FIFO read and write operations across a channel set bundle are initiated such that a difference between read and write pointer signals is the same in each channel set.

Abstract: Techniques, systems and computer program products are disclosed for providing sensor mapping. In one aspect, a method includes receiving input from a user. The received input includes at least one of motion, force and contact. In addition, a sensor signal is generated based on the received input. From a choice of data structures a data structure associated with a selected application having one or more functions is identified. The data structure indicates a relationship between the generated sensor signal and the one or more functions of the selected application. The generated sensor signal is selectively mapped into a control signal for controlling the one or more functions of the selected application by using the identified data structure.

Abstract: A method of filtering image data is described. In one embodiment, the method includes storing in line buffers image data corresponding to a plurality of rows of an image; filtering image data on one row of multiple of rows; and filtering image data on another row of the multiple rows without changing the image data stored in the line buffers between filtering image data on the one row and filtering image data on the another row.

Abstract: Various optical isolator embodiments are disclosed. Embodiments comprise a waveguide section utilizing materials that induce a propagation constant shift that is propagation-direction-dependent. Embodiments are characterized by a cutoff frequency for forward propagating waves that is different than the cutoff frequency for reverse waves; the dimensions and direction of magnetization of the waveguide can be tailored so that, in a particular embodiment, the cutoff frequency for forward propagating waves is lower than the cutoff frequency for reverse waves. A particular embodiment is constructed as a single-mode waveguide on a substrate. The cross-section of the waveguide is inhomogeneous in terms of materials. At least one part of the cross-section is a non-reciprocal magneto-optic medium, which has nonzero off-diagonal permittivity tensor components. This inhomogeneity induces a propagation constant shift, which is propagation-direction-dependent.

Abstract: Method and apparatus are disclosed related to testing and testability of adaptive equalization circuitry. Where an equalization circuit is provided in an IC, a modified internal loopback provides a testing signal. A local comparator circuit with flexible connectivity offers analog signal testing analysis in conjunction with a low-cost external tester. Flexible use and connectivity of the comparator and external connection points, and block isolation circuitry make accurate, faster, and lower cost testing methods possible.

Abstract: An apparatus for producing a word of a de-interleaved sequence of bits from a sequence of bits stored in a memory is described. In one embodiment, the apparatus includes a read circuit for selecting bits of the stored sequence and forming the selected bits into a word, and a logic network arranged to produce the word of the de-interleaved sequence by concatenating sections of a plurality of words produced by the read circuit. The technique can also be used to achieve interleaving, rather than de-interleaving, of a data sequence.

Abstract: The present invention, in an example embodiment, provides a special-purpose formal language and translator for the parallel processing of large databases in a distributed system. The special-purpose language has features of both a declarative programming language and a procedural programming language and supports the co-grouping of tables, each with an arbitrary alignment function, and the specification of procedural operations to be performed on the resulting co-groups. The language's translator translates a program in the language into optimized structured calls to an application programming interface for implementations of functionality related to the parallel processing of tasks over a distributed system. In an example embodiment, the application programming interface includes interfaces for MapReduce functionality, whose implementations are supplemented by the embodiment.

Abstract: A packet format converter (PFC) that can be programmed to perform any one of a multiple number of different packet format conversions is described. According to one embodiment, the PFC includes a pattern state machine and a pattern memory coupled to the pattern state machine. The pattern memory stores pattern memory data including pointer information. The pointer information is either for writing data to be input into the PFC or reading data to be output by the PFC. The pattern state machine is programmed based on the pattern memory data. Also in one embodiment, the PFC further includes a backpressure control for issuing ready and valid signals for the PFC, wherein the ready signal indicates whether the PFC is ready to accept input data and the valid signal indicates whether the PFC has valid data to output.

Abstract: Methods and structures for implementing repairable input/output (IO) circuitry in an integrated circuit (IC) arc disclosed. One embodiment of the present invention includes repairable IO circuitry along a right, left, or inner column of an IC. Another embodiment includes repairable IO circuitry along a top, bottom, or inner row of an IC. In one embodiment, normal and redundant mode routing is provided between IO buffer circuits and IO register circuits. In another embodiment, normal and redundant mode routing is also provided between IO register circuits and routing to core regions of the IC. One embodiment provides normal and redundant mode routing between two or more IO registers that may span more than one row and/or more than one IO block. One embodiment provides normal and redundant mode routing for different types of IO registers. In some embodiments, redundant mode IO connections shift along with redundant mode connections in a core logic region of the IC.

Abstract: Methods and circuitry for distributing and synchronizing a divided clock signal in an electronic device are disclosed. In one aspect of an embodiment, a series of registers distributes the divided clock signal and the series of registers is clocked by a full-speed clock signal from which the divided clock signal is derived. In another aspect, the divided clock signal and the full-speed clock signal are distributed to IO circuitry of the electronic device. In yet another aspect, the divided clock signal is also distributed to circuitry in a core of the electronic device.

Abstract: The invention relates to data processing apparatus and methods for method oriented invocation (MOI) of data processing service modules. MOI Adapters and methods interface compound messages with service modules that process them, advantageously reducing memory and processing time utilization. Compound messages may be progressively parsed and processed, identifying the constituent information items needed by a service module and invoking the service module when all needed information items are available, without using resources to maintain and process superfluous message data. Multiple service modules may be addressed by a single MOI Adapter.

Abstract: A sample rate converter in which filtering is decomposed into phases as permitted by zero padding is described. The outputs of the phases are issued in the correct sequence to provide the resampled sequence.

Abstract: A transmitter that includes a first phase locked loop (PLL) and a second PLL coupled to the first PLL is described. In one implementation, the first PLL is an inductance-capacitance (LC) type PLL and the second PLL is a ring type PLL. Also, in one embodiment, the transmitter further includes a PLL selection multiplexer coupled to the first and second PLLs, where the PLL selection multiplexer receives an output of the first PLL and an output of the second PLL and outputs either the output of the first PLL or the output of the second PLL. In one implementation, a control signal for controlling selection by the PLL selection multiplexer is programmable at runtime. In one implementation, the transmitter of the present invention further includes a clock generation block coupled to the PLL selection multiplexer, a serializer block coupled to the clock generation block and a transmit driver block coupled to the serializer block.

Abstract: Clock data recovery circuitry with a high speed level shifting circuits and methods are disclosed. One embodiment provides clock data recover with a high speed level shifting circuit that uses an input signal to generate two intermediate signals and uses the intermediate signals to generate an output signal such that voltage stress on individual devices within the level shifting circuit is minimized. In one embodiment, the level shifter includes a first driver and second driver coupled in parallel to provide intermediate signals to an output driver. In a particular aspect, individual transistors of the output driver are subject to voltage stresses that are less than the peak-to-peak amplitude of the output signal. In one embodiment, the first driver includes an n-channel metal oxide semiconductor (“NMOS”) cascode circuit, the second driver includes a p-channel metal oxide semiconductor (“PMOS”) cascode circuit, and the output driver includes a complementary metal oxide conductor (“CMOS”) inverter stage.

Abstract: Read interface circuitry is disclosed that facilitates using a source-synchronous clock signal to calibrate the read interface. In one embodiment, configurable read interface circuitry allows a particular read path to be configured for use in calibrating a read interface of the destination device. In particular, a plurality of read paths are provided, each read path having a configurable multiplexor (“mux”) coupled to a capture register of the read path such that the mux can be configured to select either an input coupled to an inverted output of the capture register or an input coupled to a prior register in the read data path. When the inverted output of the capture register is selected, a source-synchronous clock signal (e.g., DQS or delayed DQS signal) provided at the capture register's clock input results in a toggle signal at the capture register's output. In one embodiment, that toggle signal is provided to a re-sync register clocked by a re-sync clock signal.

Abstract: Circuitry and methods are disclosed for capturing data from a double-data rate signal received from a source circuit, converting the double-data rate signal to single and/or half rate data signals, and re-synchronizing the data to the destination circuit's clock signal. In one embodiment, a first set of registers converts a double-data rate signal synchronized to a full-rate clock signal to two single-data rate signals. A second set of registers converts the single-data rate signals to four half-data rate signals. A third set of registers synchronizes the half-rate data signals to a half-rate clock signal.

Abstract: A delay circuit that includes a first delay cell oriented in a first orientation and a second delay cell oriented in a second orientation is described. In one embodiment, the first orientation is perpendicular to the second orientation. More specifically, in one embodiment, the first orientation is vertical and the second orientation is horizontal.

Abstract: Methods and circuitry for distributing and synchronizing a divided clock signal in an electronic device are disclosed. In one aspect of an embodiment, a series of registers distributes the divided clock signal and the series of registers is clocked by a full-speed clock signal from which the divided clock signal is derived. In another aspect, the divided clock signal and the full-speed clock signal are distributed to IO circuitry of the electronic device. In yet another aspect, the divided clock signal is also distributed to circuitry in a core of the electronic device.

Abstract: A phase shift circuit that includes two, rather than four, delay chains and corresponding selectors is described. This provides a significant area savings and reduces the intrinsic delay of the phase shift circuit, which is particularly beneficial for embodiments in which there is no intrinsic delay matching. In one implementation, the phase shift circuit includes a first delay circuit and a matching delay circuit. The first delay circuit provides a first delay that includes a first intrinsic delay and a first intentional delay. The delay matching circuit provides a matching delay that matches the first intrinsic delay. In one implementation, the phase shift circuit also includes a second delay circuit to provide a second delay that includes a second intrinsic delay and second intentional delay, where the second intrinsic delay matches the first intrinsic delay and the second intentional delay is half as long as the first intentional delay.