Abstract: An antenna is provided including first and second strip resonant elements, a dielectric and a metal cover. The first strip resonant element has an F-shaped area that lies in a first plane. The second strip resonant element has an L-shaped area that lies in a second plane that is parallel to the first plane. The second strip at least partially underlies the first strip. The dielectric is positioned between the first and second strips. A metal cover is provided. Part of the metal cover is positioned perpendicularly to the first and second strips so as to provide electromagnetic shielding for the first and second strips.

Abstract: A low-voltage multipath-miller-zero-compensated operational amplifier is disclosed which includes a class AB front stage and a class AB back stage. The front stage has an inverted input, a non-inverted input, an inverted output, and a non-inverted output. The back stage has an output and input, which input is connected to the non-inverted output of the front stage. The output of the back stage is connected to the inverted output of the front stage. A capacitor is coupled in a feedback loop between the output and inverted input of the back stage. An operational amplifier in accordance with the present invention is particularly well-suited for use in switched-capacitor filters, continuous-time filters, microwave medical applications and general purpose amplification applications.

Abstract: In a CMOS device uses a thin oxide film as a gate dielectric film, gate electrode plasma etching frequently induces gate dielectric damage. This invention discloses a process which can form a damage free gate dielectric even though there is plasma nonuniformity during gate electrode etching. In this invention, a thin polysilicon layer is formed on the gate dielectric (gate oxide) layer and a thin oxide layer (not gate oxide) is formed on the thin polysilicon layer. The thin oxide layer (not gate oxide) is then patterned and etched to expose portions of the thin polysilicon layer. A thick polysilicon layer used to form the gate electrode is subsequently deposited. The thick polysilicon layer contacts the exposed portion of the underlying thin polysilicon layer, but is otherwise separated from the thin polysilicon layer by the thin oxide. The thin polysilicon layer is patterned and etched using a plasma etching process. The thin oxide (not the gate oxide) acts as an etching stop.

Abstract: A character recognition system includes a character input device, such as a stylus and tablet or optical scanner, for receiving inputted characters, and a processor. The processor determines which of a number of model characters best matches the inputted character. To that end, the processor compares each inputted character to each of a plurality of classes into which the model characters are organized. Specifically, the processor extracts a feature value vector from the inputted character, and compares it to the mean feature value vector of each class. The processor recognizes the inputted character as the model character corresponding to the mean feature value vector which is closest to the feature value vector of the inputted character. The processor also constructs the database from multiple specimens of each model character. The processor organizes the specimens of each model character into multiple classes. The processor then determines the mean feature value vector of each class.

Abstract: A method and apparatus for reducing program clock reference (PCR) jitter in transport packets of a transport stream compliant with MPEG-2 or another suitable audio-video encoding standard. The PCRs from a given single program transport stream (SPTS) of a multi-program transport stream are processed in a phase-locked loop (PLL) to generate dejittered PCRs for that SPTS. The PLL for a given SPTS receives as inputs the PCRs from that SPTS and a cycle count for each PCR indicative of the number of asynchronous clock cycles counted since the previous PCR. The PLL generates a given dejittered PCR as a function of the previous dejittered PCR, the cycle count for the given PCR, and a clock frequency mismatch estimate for the given program clock. The clock frequency mismatch estimate is generated by filtering a sequence of jitter estimates, each corresponding to the difference between a previous PCR and its corresponding dejittered PCR.

Abstract: A latch circuit has an enable circuit responds to clock pulse levels of a first polarity by outputting an enabling voltage of a second polarity opposite to the first polarity. The latch circuit also has first and second inverters which each have an output, a first biasing input connected to a first polarity voltage, a first input, a second a biasing input receiving the enabling voltage from the enable circuit and a second input. When enabled by the enabling voltage, each inverter drives its respective output to a voltage of the first polarity in response to receiving a signal of the second polarity at its first input. Alternatively, when enabled, each inverter drives its respective output to a voltage of the second polarity in response to receiving a signal of the first polarity at its second input. The first input of the first inverter receives, between the leading and trailing edges of the first polarity clock pulse levels, a signal to be stored.

Abstract: A system and process are provided for controlling congestion at a node of an asynchronous transfer mode (ATM) communications network. The process and system utilize fuzzy logic in determining whether or not to "admit," i.e., allocate a virtual channel (VC) for, new communications (or calls) to the node. Fuzzy logic is also use to control the rate cells are transmitted to the node for communications already "admitted," i.e., for which a VC has already been allocated. The fuzzy logic rules for bandwidth estimation in admission control may be developed from an "equivalent capacity" model. The fuzzy logic rules for adjusting cell transmission rates may be developed from a "two-threshold" congestion control model.

Abstract: A bidirectional buffer circuit is provided with a terminal, an input buffer, a steady state output driver and a strong output driver. The input buffer is for receiving an input signal from the terminal. The steady state output driver includes a weak driver for driving the terminal to a first voltage corresponding to a first particular logic value of the output signal. The weak driver has a limited driving capacity that can be out-driven by the input signal. The strong output driver is for driving the terminal to the first voltage. The strong output driver has a greater driving capacity than the weak output driver. Enable circuitry is also provided. The enable circuitry includes at least one delay circuit with a particular delay period. The enable circuitry enables the strong output driver in response to a transition of the output signal from a complement of the first logic value to the first logic value. However, the enable circuitry only enables the strong driver during the delay period of the delay element.

Abstract: A fuzzy reasoning system separately manages fuzzy rule groups, and fuzzy sets each including a plurality of membership functions. When executing fuzzy reasoning, the system selects one fuzzy rule group and at least one fuzzy set in conformity with a situation at that time and combines them. Thereafter, it executes the reasoning for fact information. This arrangement facilitates the building of a flexible fuzzy reasoning system which can confirm to varying situations. In another aspect, the separate management of the fuzzy rule groups and the fuzzy sets allows the selection of only any desired membership function of the fuzzy set to obtain a grade of membership based on the fact information.

Abstract: A method is disclosed for interfacing a video storage system, such as a disk array, and a video stream application executing on a computer network or stand-alone system. The interface provides a method for storing video stream data by allocating storage space in units of stripes and for accessing the data in units of fixed length segments, wherein each stripe includes one fixed length segment from each disk of the array. The interface also queues submitted I/O transaction requests so that I/O transactions requested on a current I/O cycle i are not performed until the next I/O cycle i+1. The I/O transactions thus queued are performed in an order which permits a maximum number of I/O transactions to be performed each I/O cycle, regardless of the order in which they were submitted. In addition, the interface also queues the submitted I/O transaction requests so that the completion of an I/O transaction on a current I/O cycle i is not returned until the next I/O cycle i+1.

Abstract: A circuit for implementing a neural network comprises a one dimensional systolic array of processing elements controlled by a microprocessor. The one dimensional systolic array can implement weighted sum and radial based type networks including neurons with a variety of different activation functions. Pipelined processing and partitioning is used to optimize data flows in the systolic array. Accordingly, the inventive circuit can implement a variety of neural networks in a very efficient manner.

Abstract: A method and apparatus for use in a set top box processing system to permit simultaneous utilization of two system clocks in applications in which certain processing system elements utilize one system clock operating at a non-integer multiple of another system clock used by other processing system elements. A synchronous phase detector is used to generate a clock enable signal suitable for use in a pipeline structure to facilitate data transfer between the different elements of the processing system. The clock enable signal includes phase information extracted from the first and second clock signals, and is suitable for use in driving one or more multiplexers in a pipeline structure or other state-based logic device to thereby allow data transfer between an element of the processing system operating at the first clock rate and an element operating at the second clock rate.

Abstract: A method and apparatus for providing power management functions in a computer or other electronic system which includes a primary power supply, a trickle power supply and a battery back-up power supply. A power management circuit includes a storage element which stores an indication of the current turn-on or turn-off condition of the primary power supply. The power management circuit also includes a group of logic gates which process signals which are supplied to the storage element under normal operating conditions to control the turn-on or turn-off condition of the primary power supply. The power management circuit senses when the trickle supply is deactivated due to a line power failure or the like, and subsequently switches the power supply inputs of the storage element and certain of the logic gates from the trickle supply to the battery back-up supply.

Abstract: A method and apparatus for recording and replaying variable speed data uses a rotating drum device. When information to be recorded is presented to the transfer rate of the information, be recorded is determined. If this information is not presented at a standard information transfer rate (N), it is converted to that standard rate. If the information not only is not at the standard rate N, but is outside a predetermined amount from that standard rate, the travel speed of the magnetic medium is slowed and the activation sequence of the magnetic recording head is altered. In the case where the information to be recorded is at a rate outside of the predetermined rate, the magnetic medium travel speed is reduced from the standard speed (L/T) in relation to the information transfer rate of the information to be recorded. If the tape speed is reduced to L/XT, then the activation sequence is every Xth head.

Abstract: The present invention relates to a process and to a device for the rolling of bands (B) with uneven thickness and/or length distribution over their width by using at least one control roller (5, 9, 21, 27, 41, 43) located on the inlet and/or outlet side of a mill (W, W', W") and capable of swiveling in its position relative to the band (B), making it possible in case of minor disturbances, independently of the existing operating conditions, to compensate for the running of a band caused by unevenness in the thickness and/or length distribution over the width of the band. This is achieved according to the invention in that the distribution of the tensile stress over the width of the band (B) is detected with at least one measuring device (7, 11, 25) and in that the control roller (5, 9, 21, 27, 41, 43) is adjusted in function of the detected distribution of tensile stress until the detected distribution of tensile stress is equal to a desired value.

Abstract: A floating gate E.sup.2 PROM cell is provided with a poly silicon floating gate having a pointed, sloped edge. A poly oxide is disposed on the pointed, sloped edge of the floating gate. A select gate is disposed on the poly oxide. The select gate overlaps the pointed, sloped edge of the floating gate. The floating gate, poly oxide, and select gate cooperate so that electrons tunnel according to enhanced Fowler Nordheim tunnelling from a point of the pointed, sloped edge of the floating gate, through the poly oxide and into the select gate.A simple process is also provided for fabricating an E.sup.2 PROM cell including the step of forming a nitride layer on a poly silicon layer. The nitride layer is patterned, using a photo-lithographic technique, to form an exposed poly silicon layer surface window. The exposed surface window of the poly silicon layer is then oxidized using a LOCOS (local oxidation of silicon) process to form a poly oxide region.

Abstract: A level shifter is provided with first and second steady-state drivers and transient driver circuitry. Each steady-state driver includes a low enable input, a high enable input and an output. Each steady-state driver outputs from its respective output a low voltage level signal when an enabling voltage level is received at its low enable input and a disabling voltage is received at its high enable input. Furthermore, each steady-state driver outputs from its output a first high voltage level signal, that is higher than a second high voltage level of an input signal, when a disabling voltage level is received at its low enable input and an enabling high voltage level is received at its high enabling input. The high enable input of the first steady-state driver is connected to the output of the second steady-state driver. The high enable input of the second steady-state driver is connected to the output of the first steady-state driver.

Abstract: In accordance with a preferred embodiment of the invention, the wordline turn on voltage in an SRAM array is suppressed (e.g., maintained at or below 4.5 volts). This is accomplished by connecting a regulated voltage supply output to the wordline. The regulated voltage supply has a transfer function such that the Vccr (the output of the regulated voltage supply) does not exceed a threshold such as 4.5 volts. For example, the transfer function may be:Vccr=Vcc for Vcc<4.5 voltsVccr=4.5 volts for Vcc.gtoreq.4.5 voltswhere Vcc is the power supply voltage.As indicated above, the power consumed in an SRAM array is proportional to the selected wordline voltage. In accordance with the present invention, the power consumption will be generally unchanged when Vcc exceeds 4.5 volts.

Abstract: Speech synthesizer systems avoid the need for a multi-path address bus coupling to a CPU by provision of serial interfaces requiring a total of only two or three signal paths to a CPU. By use of a counter circuit or shift register working in cooperation with a modified trigger signal circuit, a serially encoded control signal is internally converted to binary type signals which are coupled via an internal address bus to a speech synthesis unit for production of selected speech segment output signals.