Abstract: An open bond detection circuit is provided for verifying the continuity through a bonding wire connected between an external pin and a bonding pad of an integrated circuit by monitoring the potential developed across a metal conductor connected between the bonding pad and the power supply conductor. An output signal is provided having a first state upon detecting substantially zero potential difference across the metal conductor and a second state when detecting a non-zero potential difference across the metal conductor. The first state of the output signal with substantially zero potential difference reflects an open bond between the external pin and bonding pad, while the second state of the output signal with non-zero potential difference indicates the bonding wire is intact.

Abstract: An artificial neuron is provided using a simple distance calculation between the input signal vector and the synapse weight signals for providing an output signal. A difference signal is developed by subtracting a weight signal from an input signal. The difference signal is processed through a weighting function having a predetermined polarity and accumulated for providing the output signal of the neuron. A digital embodiment is supported with a memory circuit for storing the digital weights and a memory lookup table or possibly a multiplexer circuit for weighting of the difference signal. An analog embodiment uses a plurality of comparators responsive to the input signal vector and the weight signals for providing the output signal of the neuron as the absolute value of the difference of the input signal vectors and the weight signals.

Abstract: A negative feedback loop, including a two collector I.sup.2 L gate having one collector returned to the input of the gate and forcing a reference current into the other of the two collectors of the gate, is used to match the current at the collector of the injector of the gate to the reference current. The feedback loop further includes a current source for sourcing the reference current and a pair of cascoded emitter follower transistors coupled between the current source and the injector input of the gate such that the feedback loop will regulate the current through the injector to be equal to the reference current. The injector input of the gate of the feedback loop can be coupled to the injector inputs of similar I.sup.2 L gates to be biased therefrom such that the injector currents are well controlled.

Abstract: A current mirror having an input and an output, comprises a diode coupled to the input to which an input current is supplied for providing a bias potential thereacross; an output transistor having an emitter, base and collector, said base and said emitter being coupled respectively across said diode and said collector being coupled to the output, said output transistor being responsive to said diode means for providing an output current the magnitude of which is proportional to said input current; and a compensation circuit coupled to said base of said output transistor and being responsive thereto for producing an output current that is injected at the input of the current mirror for cancelling base current errors caused by the base current of said output transistor.

Abstract: A control circuit having slope compensation includes a current reference circuit for providing a reference current at an output. A resistor is coupled to the current reference circuit for varying the reference current. A current mirror circuit has a plurality of outputs, and an input which is coupled to the output of current reference circuit for receiving the reference current. A capacitor is coupled between a first one of the plurality of outputs of the current mirror circuit and a first supply voltage terminal. A charging/discharging circuit is coupled to the capacitor and to a second one of the plurality of outputs of the current mirror circuit for charging the capacitor to a first predetermined voltage at a first rate and discharging the capacitor to a second predetermined voltage at a second rate wherein the signal appearing across the capacitor is a ramp voltage signal.

Abstract: A phase lock loop for use in gate array applications with fixed transistors geometries maintains a predetermined phase delay between an input signal and an output signal. The phase comparison cycle operates over multiple periods of the input signal for increasing the operating frequency and simplifying timing considerations throughout the phase lock loop. A phase detector circuit detects a predetermined phase difference between the input signal and the output signal and provides a control signal and a clock signal at different transitions of the input signal. An up/down counter provides a count value migrating within a range of values in response to the control signal at the occurrence of the clock signal. The counter value selects a tap point of a delay line having signal inverter resolution for delaying the input signal and maintaining the predetermined phase relationship between the input signal and the output signal of the phase lock loop.

Abstract: A compressor with a DC bias control circuit is provided. The DC bias control circuit provides a predetermined DC current to a variable gain stage of the compressor circuit such that when the input signal to the compressor is substantially equal to zero, the variable gain stage is biased by the DC current and provides a DC feedback path for the compressor.

Abstract: A comparator circuit is provided compatible with CMOS logic levels for the input signal and including a substantially zero standby current when the input signal is initially less than the upper trip threshold. The trip threshold follows a bandgap voltage with a zero temperature coefficient, while hysterisis is provided with the upper and lower trip thresholds. An alternate embodiment of the comparator circuit provides a selectable zero temperature coefficient for the trip threshold as a ratio of emitter resistors while maintaining the hysterisis with the upper and lower trip thresholds.

Abstract: An artificial neural network is provided using a modular, self-organizing approach wherein a separate neural field is contained within each module for recognition and synthesis of particular characteristics of respective input and output signals thereby allowing several of these modules to be interconnected to perform a variety of operations. The first output and second input of one module is respectively coupled to the first input and second output of a second module allowing each module to perform a bi-directional transformation of the information content of the first and second input signals for creating first and second output signals having different levels of information content with respect thereto. In the upward direction, the first low-level input signal of each module is systematically delayed to create a temporal spatial vector from which a lower frequency, high-level first output signal is provided symbolic of the incoming information content.

Abstract: A detection circuit including a first and second sensing circuits detects the presence of load current provided by a utilization circuit to which the detection circuit is coupled to provide an output current that is proportional to the load current. A fraction of the load current that is sourced from the utilization circuit flows through the first sensing circuit the latter of which then provides an output current proportional to the fractional load current. Similarly, a fraction of load current that is sunk by the utilization circuit flows through the second sensing means which provides an output current proportional to the fractional load current.

Abstract: An amplifier having an input and output stage for providing drive current to a load coupled thereto includes circuitry that senses when an input signal is applied to the amplifier and is responsive thereto for providing an enabling signal at an output thereof and current regulator circuitry that supplies a low drain current to bias the stages when the amplifier is in a quiescent operating mode absent an applied input signal and that is responsive to the enabling signal for increasing the current supplied to the stages to bias the same in a high bias drain current operating mode.

Abstract: A circuit which provides a threshold voltage to a single-ended operated diode load emitter coupled logic circuit includes a transistor having an emitter coupled to an output at which the threshold voltage is produced, a collector coupled to a positive supply conductor and a diode coupled between the positive supply conductor and the base of the transistor. A current source is coupled to the emitter of the transistor which sinks a current that is equal to the "tail" current of the logic circuit. The magnitude of the threshold voltage produced is equal to a value that lies midway between the logic output voltage swing developed across the diode loads of the logic circuit.

Abstract: A dectector circuit responsive to a current suppled to an input thereof provides an output signal when the magnitude of the current exceeds a predetermined threshold level includes a multi-collector transistor having a first one of its collectors connected to the base thereof and an emitter coupled to the input. A diode formed by a diode-connected transistor is coupled to the first collector of the multi-collector transistor. A second transistor is provided having its collector coupled to the second collector of the multi-collector transistor, a base coupled to the first collector and an emitter which is coupled to a pair of series connected resistors. The second transistor is operated at a lower current density than the diode-connected transistor such that the former operates in a saturated condition until such time that the input current exceeds the threshold level to produce the output signal.

Abstract: This invention relates to transistor breakdown protection circuits for use in high voltage circuitry. This inventions relates more particularly to memory systems such as Electrically Erasable Programmable Read Only Memory (EEPROM), or Non-Volatile Random Access Memory (NVRAM) which require high voltages for write and erase operations.

Abstract: An integrated amplifier that can be use as a standard cell which includes a differential input stage and an output stage to provide an increased input common mode range. The differential input stage includes a pair of differentially configured PMOS transistors coupled to a differential-to-single ended converter comprised of a pair of NMOS transistor. A PNP transistor is formed in the integrated circuit having its base-emitter junction coupled between the drain and gate of one of the NMOS transistors to thereby establish therewith a voltage at the drain of the PMOS device coupled to the inverting input of the amplifier sufficient to maintain the latter in its linear operating range as the input thereto is common moded to ground.

Abstract: A voltage translator circuit is responsive to applied ECL input signals for providing corresponding CMOS level logic output signals therefrom. The voltage translator circuit includes a pair of substantially identical translator circuits each having an input coupled to an input of the voltage translator circuit and which are supplied a regulated voltage such that the operation thereof is substantially independent of negative power supply variations and temperature. An output stage is coupled between the output of one of the pair of translator circuits and the output of the voltage translator circuit while the output of the other translator circuit is coupled to the output of the voltage translator circuit in order to provide the CMOS level logic output signals.

Abstract: An active integrated termination circuit for providing a predetermined impedance at an output includes first and second resistors each having one end of which is commonly connected to the output. A first switching element is coupled between the other end of the first resistor and a first power supply conductor and is responsive to control signals for selectively coupling and de-coupling the first resistor to the first power supply conductor. A second switching element is coupled between the other end of the second resistor and a second power supply conductor and is responsive to the control signals for selectively coupling and de-coupling the second resistor to the second power supply conductor. The first and second resistors are polycrystalline silicon resistors and are trimmed to predetermined values by pulsing a high current unilaterally therethrough.

Abstract: A circuit for generating voltages having values proportional to the threshold voltages (V.sub.T) of n-channel transistors used in the circuit comprises a current mirror M.sub.2, M.sub.3 having a reference current input generated from a reference voltage of value 2V.sub.t by an n-channel transistor M.sub.1. The output reference voltage of value 2V.sub.T by an n-channel transistor M.sub.4 whose gate is coupled either to its drain, for output voltages greater than V.sub.T, or to the gate of transistor M.sub.1 for output voltages less then V.sub.T.

Abstract: A TTL output driver is provided which increases the high level of the output signal thereof. The first and second emitters of a first transistor are coupled to the collector and base of a second transistor, respectively, the emitter and collector of which are coupled to the output of the TTL output driver and through a series combination of diode and resistor to a source of operating potential respectively. The output voltage is increased by reducing the base current drive of the first transistor required to achieve the desired output current.

Abstract: A deglitch circuit for suppressing transient signals that appear at an output node includes a bias circuit for providing a bias signal; a transistor having its collector-emitter conduction path coupled in series to the output node and having a base coupled to the bias signal; and a capacitive element coupled between the output node and the base of the transistor for rendering the transistor conductive in response to a transient signal such that a low impedance circuit path is presented to the transient signal.