Abstract: A power supply monitoring circuit for operating in a plurality of modes comprising first and second single input comparators coupled to first and second inputs, respectively, for sensing the voltage levels thereof. A reference circuit for generating a reference voltage at a first output. A programming circuit coupled to the outputs of the first and second single input comparators and being responsive to a third input for providing the selection of plurality of operation modes and for providing second and third outputs which are function of the voltage levels appearing at the first and second inputs.

Abstract: A circuit having first and second inputs and first and second outputs includes a differential receiver circuit responsive to the first and second inputs for providing corresponding output logic signals at the first and second outputs. A tri-state detection circuit responsive to the first and second inputs and having an output for providing a first predetermined voltage to the differential receiver circuit when the first and second inputs are in a normal mode and for providing an increased second predetermined voltage to the differential receiver circuit when the first and second inputs are in a tri-state mode wherein oscillation of the differential receiver circuit is prevented and the outputs are forced to known logic states while the noise margin of the differential receiver is increased without a sacrifice in common mode range.

Abstract: An active dummy load substantially reduces skews for input signals of a CML or an ECL series gate by generating a selectable capacitance that adjusts the delay time of the output signal in relation to the changing of the input signal to one of two states.

Abstract: A relaxation oscillator is disclosed which includes first and second currents for charging and discharging a capacitor wherein the slew rate of the dynamic voltages developed at the terminals of the capacitor remain substantially constant for each frequency of operation which desensitizes the oscillator to the effects of the inherent stray capacitance, and improves the accuracy of the output frequency. A circuit monitors the dynamic voltage across the capacitor and inverts a control signal at opposite polarities of a particular threshold. A bistable circuit provides first and second complementary output signals in response to the control signal from the circuit. The first and second complementary output signals drive a pair of switching transistors which alternate the direction of current flowing through the capacitor so as to provide smooth voltage transitions at the terminals of the capacitor.

Abstract: A comparator circuit with hysteresis does not require any bias current as long as the input signal applied thereto is less than a lower threshold value of the comparator. The comparator includes a current source for providing a plurality of currents when enabled, a Zener diode coupled to the current source for initially enabling the former as the input signal exceeds an upper threshold value, an output circuit which when rendered operative is placed in parallel to the Zener and disables the same while maintaining the current source enabled and providing an output signal from the comparator, and an amplifier responsive to the current source which renders the output circuit operative as the magnitude of current sourced thereto exceeds a predetermined value.

Abstract: A combinational static CMOS logic circuit for providing a plurality of basic two-input logic functions with reduced complexity and integrated circuit area. The combinational static CMOS logic circuit provides either a NAND or an XOR output at a first output terminal and a NOR output at a second output terminal. A configuration input terminal is utilized for selecting between the NAND or the XOR output being provided at the first output terminal. In an alternate configuration, the combinational static CMOS logic circuit provides either a NOR or an XNOR output at a first output terminal and a NAND output at a second output terminal.

Abstract: A high voltage bridge interface circuit is provided for AC and brushless DC motor control having a high voltage isolation circuit and drive circuits which simplify the high voltage interface and reduce the total system integration effort. The isolation circuit provides the high voltage unilateral isolation between the control circuit and the high voltage power supply conductors, while the drive circuits improve the noise immunity at the gate termimals of the power MOSFET bridge. The high voltage bridge interface circuit is partitioned by providing the high voltage interface within one IC thereby permitting the integration of the discrete components of the power MOSFET drive circuits and simplifying the overall system integration.

Abstract: A substrate injection clamp uses a pre-existing NPN open-collector transistor to provide substrate protection for the parasitic diode formed between the collector of the transistor and the P-substrate of the IC. The NPN transistor is responsive to a control signal for rendering the transistor conductive and non-conductive. If a negative potential is applied to the collector, the NPN transistor operates in an inverse active mode, provided that the control signal is asserted, to source current from the emitter through the collector thereby clamping the voltage at the latter to a predetermined value less than the forward bias potential of the parasitic diode. If the control signal is not asserted, a circuit detects its absence and a provides a bias signal to the base to allow the NPN transistor to operate in the inverse active mode.

Abstract: A combined multiple memory array is disclosed which includes at least two differing types of memory arrays located next to and aligned to one another. The individual memory cells of the differing memory arrays are designed wherein the x pitches may vary in order to allow the y pitches to be substantially equal. A common set of row decoders provide common wordline decoding to the differing memory arrays. The memory arrays need not have the same number of words or bits to share the common row decoders. The column decoders may be separate for each array to account for different word sizes. A common set of column decoders is possible with equal word lengths from each array. A significant savings in silicon area may be saved by combining the multiple arrays.

Abstract: In a TV receiver including multistandard OSD circuitry a method and apparatus for positioning the display including a comparator which compares a predetermined count (position) with a count of the received horizontal frequency to provide delayed horizontal flyback pulses and a dot and column address generator which is synchronized to start with the delayed horizontal flyback pulses. Similar vertical positioning circuits are included.

Abstract: A television receiver including a MPU and OSD circuitry on a single chip. The OSD circuitry includes multisystem detection circuitry which counts the number of horizontal lines between vertical flyback pulses to determine the vertical frequency of the received standard signal and measures the time of a horizontal line using a fixed frequency signal to determine the horizontal frequency of the received standard signal and uses this information to control the outputs of a PLL to synchronize the receiver to the received standard. The PLL includes a VCO having a constant offset current applied to the control terminal to prevent alternating phases of the output control signal from the loop phase detector, which alternating phases cause jitter in the display.

Abstract: A digital to analog converter circuit produces an output voltage which includes a small error voltage floating on a larger direct current voltage component. The circuit includes a controlled current supply coupled to the emitter of an NPN transistor to which the direct current voltage component is supplied to the base thereof. The error voltage is generated by modulating the current through the transistor by controlling the current supply, independent of the voltage component supplied to its base, such that the output voltage occurring at the emitter of the transistor is a function of the difference between the direct current component and the natural log of the modulated emitter current.

Abstract: A current source regulator is responsive to an enable signal and provides at least one output current of predetermined magnitude proportional to absolute temperature. The enable signal biases a first transistor for supplying current through its collector-emitter conduction path to the common base of a string of PNP transistors, the latter of which provide the output current. The current flowing in one of the PNP transistors flows through a regulating feedback circuit, the output of which regulates the base voltage of the first transistor to control the base voltage of the PNP transistors for maintaining the current flowing through the regulating feedback circuit at the predetermined value proportional to absolute temperature.

Abstract: A TV receiver including a microprocessor and an on screen display on a single semiconductor chip. The OSD includes half dot logic and shifting to smooth the characters with a minimum of storage capacity required and the half dot logic is used in an edge enhancing circuit to generate a black surround. A simplified window generator is combined therewith to further improve the characters.

Abstract: A design and method of exhaustively verifying the boolean functionality of both combinational and sequential cells for Application Specific Integrted Circuit gate array and standard cell libraries is provided. A single integrated circuit includes a plurality of cells or macros from the library. A Gray code generator provides a plurality of Gray code signals to the cells in response to a binary counter. The binary and Gray code signals stimulate each state of each cell. A multiplexed output indicates the functionality of each state.

Abstract: An ECL transient driver discharges a capacitive load at the output of an emitter follower with a pulse whose amplitude and duration is determined by the charge on the load. A pull-up transistor is coupled to an output terminal for selectively supplying a voltage thereto in response to a first signal from a logic circuit. A pull-down transistor is coupled to the output terminal for selectively sinking a current therefrom in response to a second signal. A comparator circuit is coupled to the pull-down transistor, the logic circuit, and the output terminal, for selectively providing the second signal in response to the first signal and an output voltage on the output terminal.

Abstract: A single-ended operational amplifier uses a plurality of chopper circuits to alternately transpose matched transistor pairs for cancelling offset errors due to transistor mismatches from statistical process variations. The differential input signals are transposed while simultaneously transposing the currents in a current mirror and in the load devices. The matched devices comprising an output stage remain un-transposed since their contribution to offset error is minimal but their contribution to noise error would be substantial due to the potentially larger voltage differentials existing between them.

Abstract: A circuit for providing rapid charge and discharge of a capacitive load is utilized in conjunction with a phase detector error signal output generated in a television video demodulator system for controlling the operating frequency of the local oscillator. The circuit comprises a pair of comparators each biased to a respective threshold level whereby the first comparator provides an output signal when the error signal supplied thereto from the phase detector exceeds its threshold level and the second comparator provides an output signal when the error signal is less than its threshold level. An additional circuit is coupled to the outputs of the pair of comparators and is responsive to the first comparator for sourcing current to the capacitive load while being responsive to the second comparator for sinking current from the load. The capacitive load may be the AFC filter of an AFC loop of a television receiver wherein the local oscillator frequency is controlled by the voltage developed across the filter.

Abstract: A current switch that is responsive to logic switching control signals is used in a telephone circuit comprising a handset receive signal path and a speakerphone receive signal path for separation a received voice signal into either the handset or speakerphone receive path depending on the selected mode of operation of the telephone circuit. The current switch includes a pair of switched current mirrors and clamp circuits which are rendered active or inactive depending on the particular mode of operation. The clamp circuits maintain the dc voltage appearing at the input of each current mirror constant as the particular current mirror is switched between active and inactive states thereby inhibiting audible dc transients.

Abstract: An identification circuit for use in identifying at least two integrated circuits having the same logic function but different input/output characteristics, each circuit having first and second isolated power supply conductors. A unilateral current conducting circuit having an input and an output is coupled between the first and second power supply conductors via conductive jumpers in all but one of the identifiable integrated circuits. The conductive jumpers are removed for one integrated circuit family. The other integrated circuit families have unique combinations of a resistor and at least one serially coupled diode wherein a predetermined potential is required to induce current to flow therethrough for each family. The potential of the first power supply conductor is increased in predetermined steps until current flow is detected, or a predetermined maximum potential is reached.