Abstract: A detection circuit for sensing small capacitive changes has been provided. The detection circuit includes a dummy integrator stage that compensates for a voltage step that results from charge injection due to an existing switch in a first integrator stage. As a result, the detection circuit is insensitive to switch injection and amplifier offset voltages.

Abstract: A self-timed RAM (2) having a two-phase read and write operating cycles which comprise a precharge phase and a discharge phase and which is clocked by a clock signal. The self-timed RAM comprises control means (18, 20, 24, 22, 26, 28, 30) for initiating and controlling the precharge phase followed by the discharge phase in response to a first transition of the clock signal. The self-timed RAM further comprises logic means (30, ERRFLG) which determines when either phase of the two-phase operating cycle has not been completed before the next first transition of the clock signal and in response thereto activates an error indicating means (ERRFLG) to indicate that an error may have occurred during the RAM operating cycle. A controlling system of the RAM can then determine that an error may have occurred during the RAM operating cycle by checking the error indicating means (ERRFLG).

Abstract: An active filter circuit (10) that has a cut off frequency being substantially independent of absolute and temperature variations due to on chip resistors (R.sub.1, R.sub.2 and R.sub.3) has been provided. The active filter includes a transconductance gain amplifier (16) having first and second currents (I.sub.B and I.sub.E) the ratio of which are controlled such that the absolute and temperature effects of any on chip resistors of the active filter circuit are removed. The ratio of the first and second currents of the transconductance gain amplifier are controlled by a circuit that generates third and fourth currents (I.sub.b and I.sub.e) which are a function of a bandgap voltage. The circuit then utilizes the third and fourth currents and provides, to the transconductance gain amplifier, a current that is substantially equal to the ratio of square of the third current to the fourth current, and a current substantially equal to the fourth current.

Abstract: A speakerphone with a varying gain current mirror circuit is provided. The varying gain current mirror circuit is within the DC control loop of the speakerphone such that by varying the gain of the current mirror circuit, the attenuation range of the speakerphone is correspondingly varied.

Abstract: A high impedance output driver stage (16) for reducing loading on a gain stage (18) which drives an output stage (19). The output stage (19) is responsive to an input current. A current sense circuit (21) senses current of output stage (19). The current sense circuit (21) outputs a current proportional to the current sensed in the output stage (19). A current source circuit (22) is responsive to the current output by the current sense circuit (21) and outputs a current substantially equal to the input current of the output stage (19) thereby reducing loading on the gain stage (18).

Abstract: A rule based floorplanner for a macrocell array having a plurality of predetermined macrocells. The floorplanner uses a net list (23), a macrocell list (26), and a list of design constraints (31) and characteristics of the base array itself to derive an initial Burain score. A trial floorplan is attempted (33) and checked against a list of theoretical rules (39) and a list of empirical rules (38) to determine a measured Burain score (36) which accurately indicates the difficulty which can be expected when completing the design.

Abstract: A transistor package for use in common base linear, amplification applications includes a base flange member to which an insulating substrate is disposed wherein the bottom surface of the substrate is metalized to provide electrical contact to the flange member. Opposing ends of the substrate are edge metalized to conductively contact the bottom surface while the center portion of the top surface of the substrate has a selective metalized patterned formed therein and is isolated from the metalized opposing edges A metal bonding pad is formed centrally within the center portion and isolated therefrom to which the collector electrode of a transistor chip is die bonded. A lead frame comprising first and second opposing leads and a third lead adjacent to and parallel to the first lead is brazed to the center portion such that the first and second leads are insulated from the center portion while the third lead makes direct contact thereto.

Abstract: The database is provided with an audit trail for the structure types of the object instances. As a component of an object instance of the database is corrected/changed, the corrected/changed component is substituted for the original component and the original component is linked to the corrected/changed component.

Abstract: A digital voltage level translator circuit for interfacing circuitry operating at different voltages is described. An inverting digital voltage level translator circuit (11) has an input (12) and an output (13). The input is coupled to a transmission gate (18), an inverter (17), and a gate of a n-channel enhancement MOSFET (22). Transmission gate (18) is enabled by the inverter (17) when the input (12) is at a zero logic level. An output of transmission gate (18) is coupled to a gate of a p-channel enhancement MOSFET (21) and an output of a pull-up circuit (19). A zero logic level at the input (12) enables MOSFET (21) through transmission gate (18) and disables MOSFET (22) generating a one logic level at output (12). A one logic level at the input (12) enables MOSFET (22) transitioning output (13) to a zero logic level. Output (13) to a control input of pull-up circuit (19) and a zero logic level enables pull-up circuit (19) disabling MOSFET (21).

Abstract: A temperature compensated voltage regulator circuit having a first resistor (R.sub.X) disposed in the base circuit between two cascaded transistors and a second resistor (R.sub.F) coupled between the collector and base of the first of the two transistors to provide compensation for beta variations in the transistors resulting from process variables during the manufacture of the circuit.

Abstract: This invention relates to a video analog-to-digital converter (ADC) and to a method of digitizing a video analog signal. The video ADC (2) comprises a clock for providing a clock signal (HZ) which clocks a horizontal line rate, dither generating means (10) for generating a dither pattern synchronized with the horizontal clock signal. A preferred dither pattern comprises a staircase sequence of voltage steps, the voltage level of each step being constant for at least one horizontal line. The video ADC further comprises combining means for combining the dither pattern with the analog video signal, digitizing means (4, 6) for converting the combined dither pattern and video signal to a sequence of digital values and correcting means (12) coupled to the digitizing means and the dither generating means for subtracting the dither pattern from the digitized sequence of values so as to generate a sequence of digital values which represent said analog video signal.

Abstract: A DC/DC voltage converting device is obtained for boosting a DC power supply voltage to provide a higher output voltage, comprising soft start circuit 20 for gradually increasing the turning-on duration of transistor 34 in boosting circuit 30; pulse width control circuit 60 for providing a modulated pulse signal P2 to control the boosted voltage. The device further comprises boosting circuit 30 including an inductor 32, diode 36 and transistor 34. Boosting circuit 30 provides a predetermined boosted voltage higher than the power supply voltage by alternately turning on and off transistor 34. The turning-on duration of transistor 34 is gradually increased during the initial operation period by soft start circuit 20, and is controlled by modulated pulse signal P2 during a stable operation period. The device further comprises gate circuit 40 having diode 46 and transistor 44, and step up circuit 70.

Abstract: A delay line having feedback from a control circuit at the output of the delay line controls the delay line duty cycle to within a specified range. The delay line comprises at least one delay unit having control inputs to each delay unit. The output of the delay line feeds to a low-pass filter (LPF). A voltage proportional to the duty cycle of the delay line output is generated within the LPF and fed to a differential amplifier. The differential amplifier is in turn coupled to the control inputs of each of the delay units. When the voltage signal from the LPF is high (duty cycle is high), the differential amplifier will generate a signal causing the fall time of the signal propagating through the delay line to increase and rise time to decrease. This will decrease the high cycle time at the output of the delay line. When the voltage signal from the LPF is low (duty cycle is low), the differential amplifier will generate a signal causing the fall time to decrease and the rise time to increase.

Abstract: A gate driver circuit for switching a MOSFET on and off while reducing the turn off delay of the MOSFET without effecting the turn off slew rate thereof includes a low impedance circuit path between the gate and drain of the MOSFET which is responsive to a control signal for providing discharge of the gate capacitance and a controlled current discharge path for controlling the slew rate of the drain voltage. The low impedance circuit path is automatically disabled once the threshold voltage of the MOSFET is reached and the MOSFET begins to turn off as the drain voltage reaches a predetermined level. As the low impedance circuit path is disabled the controlled current discharge path fixes the slew rate or dv/dt of the drain to source voltage during turn off of the MOSFET.

Abstract: A differential amplifier avoids gain fluctuations due to process differences and changes in temperature and allows adjustability of the gain and associated frequency characteristics to desired gain values. The amplifier comprises a pair of load transistors coupled to a pair of differential input transistors. A pair of biased current source transistors assure a constant current through the differential transistors, and a pair of bias transistors supply a constant bias to the source of the load transistors. The gain is varied by varying the voltage supplied to the gates of the two load transistors. The voltage supplied to the load transistors is varied by varying the current supplied through a second pair of bias transistors. A number of current source transistors coupled in parallel vary the voltage through the second pair of bias transistors.

Abstract: A clamp circuit is described in which a video signal is capacitively coupled to an amplifier which has enabled and disabled states. An operational amplifier receives the output of the amplifier and a reference voltage and the output of the operational amplifier is fed back to the inputs of both the amplifier and the operational amplifier. The loops may be selectively disconnected and the amplifier selectively disabled so that the output of the amplifier has the same level during each of three modes namely clamp mode when the video signal is known to be black, image mode during normal operation when the video signal returns to black, and during blank mode initiated at any other desired time.

Abstract: A chopper type voltage comparator, as used in analog-to-digital converters, includes an inverter with a switch coupled between the output and an input node and a capacitor coupling the input node to a comparator input node. A signal input terminal and at least one reference voltage input terminal are connected to the comparator input terminal by alternately operated switches. A sample hold circuit is connected to the comparator input node to overcome the effects of the switches on the reference voltage.

Abstract: A circuit for interfacing with the outputs of a differential pressure sensor provides a single-ended output voltage translated in voltage level with respect to the differential voltage applied thereto from the sensor while cancelling the common mode offset voltage of the sensor so that the output voltage is independent of the common mode offset voltage. The circuit includes four operational amplifiers arranged as a differential-to-single ended converter with gain.

Abstract: A logic circuit that is responsive to applied ECL input logic signals for providing complementary CMOS logic output signals at first and second outputs includes a translation and latch circuit as well as feedback circuitry. The logic circuit includes an input buffer circuit that provides ECL differential logic signals to the translation and latch circuit, the latter of which receives a CMOS clocking pulse. The translation and latch circuit is responsive both to the clocking pulse and the differential ECL logic output signals for producing complementary CMOS control signals at first and second outputs which are latched during the duration of the clocking pulse. A feedback circuit comprising a pair of CMOS inverters each coupled respectively to the first and second outputs of the translation and latch circuit provide feedback control signals which are applied respectively to a pair of CMOS output buffer stages in conjunction with the CMOS control signals to produce the CMOS logic output signals.