Abstract: To form substrate isolation for a nonvolatile memory, floating gate polysilicon (410) is formed over a semiconductor substrate (110), then silicon nitride (130) is deposited, and then the nitride, the floating gate polysilicon and the substrate are etched to form isolation trenches (140). Dielectric (150) is formed in the trenches and over the silicon nitride. The dielectric thickness is relatively small so that the top surface (150T) of the dielectric over the trenches lies at all times below the top surface of silicon nitride. The dielectric deposition and polishing times are therefore reduced. Other embodiments are also provided.

Abstract: In some embodiments, a circuit structure comprises a semiconductor substrate, an opening passing through the substrate between a first side of the substrate and a second side of the substrate, and a plurality of conductive layers in the opening. In some embodiments, one conductive layer provides an electromagnetic shield that shields the substrate from AC signals carried by a contact pad made from another conductive layer on a backside of the substrate. The conductive layers can also be used to form capacitor/rectifier networks. Manufacturing methods are also provided.

Abstract: A semiconductor wafer is diced before thinning. The wafer is diced only part of the way through, to form grooves which are at least as deep as the final thickness of each chip to be obtained from the wafer. Then the wafer backside is etched with a dry etch, for example, atmospheric pressure plasma etch. The wafer is thinned until the grooves are exposed from the backside. The dry etch leaves the chip's backside smooth. After the grooves have been exposed, the dry etch is continued to remove damage from the chip sidewalls and to round the chips' bottom edges and corners. The grooves' aspect ratio is large to reduce the lateral etch rate of the chip sidewalls and thus allow more area for on-chip circuitry.

Abstract: A plasma apparatus separately measures multiple plasma jets upstream of where the plasma jets converge into a combined plasma stream. The separate plasma jets can be separately adjusted to place the separate jets in a configuration that provides the combined stream with desired properties for a plasma treatment. The system can include an injector for a neutral jet that becomes part of the combined plasma stream. With an injector, the positions of the plasma jets can be measured relative to the injector so that the plasma jets and the neutral jet are properly aligned to form a combine plasma stream having the properties desired.

Abstract: The present invention comprises a dynamic brake that applies restraining frictional force to a wafer in a wafer holder while the wafer holder is substantially at rest, but releases the restraining force as the processing carousel containing several wafer holders rotates about a central axis of the carousel. This dynamic brake preferably comprises a boot that passes through an opening in the wafer holder to rest on the surface of the wafer in an exclusion zone near the wafer's edge. The exclusion zone is typically no more than about 3 mm in extent. The frictional force between the boot and wafer is sufficient to prevent unwanted motion of the wafer in the holder. As the wafer holder rotates about a central axis of the processing carousel, centrifugal forces applied to the brake arising from such rotation cause the boot to pivot upward, releasing the frictional force on the wafer.

Abstract: A semiconductor wafer is diced before thinning. The wafer is diced only part of the way through, to form grooves which are at least as deep as the final thickness of each chip to be obtained from the wafer. Then, the wafer is placed into a non-contact wafer holder, and the wafer backside is blanket etched with a dry etch, for example, atmospheric pressure plasma etch. The wafer is thinned until the grooves are exposed from the backside. The dry etch leaves the chip's backside smooth. After the grooves have been exposed, the dry etch is continued to remove damage from the chip sidewalls and to round the chips' bottom edges and coners. As a result, the chip becomes more reliable, and in particular more resistant to thermal and other stresses.

Abstract: Different frames received on a first port are processed by different processing channels in parallel. The processed frames are transmitted to a second port in the same order in which they were received on the first port. The ordering is maintained using a FIFO that receives the number of a processing channel whenever a frame is dispatched to the processing channel. The processing channels are selected to provide frames to the second port in the order of the channel numbers in the ordering FIFO.

Abstract: A plasma apparatus separately measures multiple plasma jets upstream of where the plasma jets converge into a combined plasma stream. The separate plasma jets can be separately adjusted to place the separate jets in a configuration that provides the combined stream with desired properties for a plasma treatment. The system can include an injector for a neutral jet that becomes part of the combined plasma stream. With an injector, the positions of the plasma jets can be measured relative to the injector so that the plasma jets and the neutral jet are properly aligned to form a combine plasma stream having the properties desired.

Abstract: To fabricate back side contact pads that are suitable for use in a vertical integrated circuit, vias are made in the face side of a wafer, and dielectric and contact pad metal are deposited into the vias. Then the wafer back side is etched until the metal is exposed. When the etch exposes the insulator at the via bottoms, the insulator is etched slower than the wafer material (e.g. silicon). Therefore, when the dielectric is etched off and the metal is exposed, the dielectric protrudes down from the wafer back side around the exposed metal contact pads, by about 8 &mgr;m in some embodiments. The protruding dielectric portions improve insulation between the wafer and the contact pads when the contact pads are soldered to an underlying circuit. In some embodiments, before the contact pads are soldered, additional dielectric is grown on the wafer back side without covering the contact pads.

Abstract: When a search key is supplied to a content addressable memory (CAM), the CAM signals indicate which CAM entries have matched the key. These signals are provided to a weight array to select the entry of the highest priority. Each entry's priority is indicated by a weight in the weight array. The weight array processing is pipelined. In pipeline stage 0, the most significant bits (bits 0) of the weights are examined, and the highest priorities are selected based on the most significant bits. At pipeline stage 1, the next most significant bits (bits 1) are examined, and so on.

Abstract: The present invention comprises a dynamic brake that applies restraining frictional force to a wafer in a wafer holder while the wafer holder is substantially at rest, but releases the restraining force as the processing carousel containing several wafer holders rotates about a central axis of the carousel. This dynamic brake preferably comprises a boot that passes through an opening in the wafer holder to rest on the surface of the wafer in an exclusion zone near the wafer's edge. The exclusion zone is typically no more than about 3mm in extent. The frictional force between the boot and wafer is sufficient to prevent unwanted motion of the wafer in the holder. As the wafer holder rotates about a central axis of the processing carousel, centrifugal forces applied to the brake arising from such rotation cause the boot to pivot upward, releasing the frictional force on the wafer.

Abstract: In a video conferencing system, a video overlay system (160) generates a motion video signal (MV). The motion video signal incorporates an image received from a remote video conferencing system (110.2) and from a local camera (186). The video overlay system also receives a computer video signal (CV) from a local computer (140). A summing amplifier (310) in the video overlay system generates an output signal (SV) representative of the sum of the computer video signal and the motion video signal. The output signal (SV) is provided to a monitor (174) when motion video is to be displayed. Use of the summing amplifier allows a cursor (240) generated by the computer to be inserted into the motion video on the monitor screen.

Abstract: A closed caption decoder includes circuitry for processing closed caption according to the Electronic Industries Association EIA-708 and EIA-608 standards. The EIA-708 memory buffers (48) store caption data both for the EIA-708 and the EIA-608 standards. Therefore, the decoder memory requirements are reduced.

Abstract: In a burst operation, a counter receives one or more bits of a starting column address. The count signal generated by the counter is provided to column decoders. The column decoders select two columns in response to a single value of the count signal. The two columns can be at non-consecutive column addresses. Alternatively, the two columns can be at consecutive column addresses starting at an odd column address boundary. Data are transferred between the two columns and a buffer in parallel. Data are transferred between the buffer and a data terminal serially. Some embodiments are suitable for burst operations defined by standards for synchronous dynamic random access memories.

Abstract: In a nonvolatile memory, select gates are self-aligned spacers formed on sidewalls of floating/control gate stacks. The same mask (1710) is used to remove the select gate layer from over the source lines (144), to etch trench insulation in the source line regions, and to dope the source lines. The memory can be formed in and over an isolated substrate region. The source lines can be doped at least partially before the trench insulation is etched, to prevent a short before the source lines and a region isolating the isolated substrate region from below. The memory can be erased by sectors, or alternatively a chip erase operation can be performed to erase all the cells in parallel. Peripheral transistor gates can be formed from the same layer as the select gates. The select gate spacers have extensions to which low resistance contacts can be made from overlying metal lines.

Abstract: In a multi-tasking pipelined processor, consecutive instructions are executed by different tasks, eliminating the need to purge an instruction execution pipeline of subsequent instructions when a previous instruction cannot be completed. The tasks do not share registers which store task-specific values, thus eliminating the need to save or load registers when a new task is scheduled for execution. If an instruction accesses an unavailable resource, the instruction becomes suspended, allowing other tasks' instructions to be executed instead until the resource becomes available. Task scheduling is performed by hardware; no operating system is needed. Simple techniques are provided to synchronize shared resource access between different tasks.

Abstract: A first level packaging wafer is made of a semiconductor or insulating material. The bumps on the wafer are made using vertical integration technology, without solder or electroplating. More particularly, vias are etched part way into a first surface of the substrate. Metal is deposited into the vias. Then the substrate is blanket-etched from the back side until the metal is exposed and protrudes from the vias to form suitable bumps. Dicing methods and vertical integration methods are also provided. Solder or electroplating are used in some embodiments.

Abstract: To move an article in and out of plasma during plasma processing, the article is rotated by a first drive around a first axis, and the first drive is itself rotated by a second drive. As a result, the article enters the plasma at different angles for different positions of the first axis. The plasma cross-section at the level at which the plasma contacts the article is asymmetric so that those points on the article that move at a greater linear velocity (due to being farther from the first axis) move longer distances through the plasma. As a result, the plasma processing time becomes more uniform for different points on the article surface. In some embodiments, two shuttles are provided for loading and unloading the plasma processing system. One of the shuttles stands empty waiting to unload the processed articles from the system, while the other shuttle holds unprocessed articles waiting to load them into the system.

Abstract: A processor system suitable to provide an interface between networks includes a software programmable processor and a channel processor that receives data from a network and transforms data at commands from the software programmable processor. The channel can execute only a few simple commands, but these commands are sufficient for a wide range of systems. The commands include (1) a command to transmit received data, perhaps skipping some data; and (2) a command to transmit data specified by the command itself rather than the received data. The channel is fast, simple and inexpensive.

Abstract: To move an article in and out of plasma during plasma processing, the article is rotated by a first drive around a first axis, and the first drive is itself rotated by a second drive, so that the article enters the plasma at different angles for different positions of the first axis. The plasma cross-section at the level at which the plasma contacts the article is such that those points on the article that move at a greater linear velocity (due to being farther from the first axis) move longer distances through the plasma. As a result, the plasma processing time becomes more uniform for different points on the article surface. The direction of rotation of the first and/or second drive changes during processing to improve processing uniformity. The article is allowed to be processed with the plasma only during one-half of each revolution of the second drive.