Abstract: A non-volatile programmable latch (210) has a fuse (F1) connected between a non-ground voltage terminal (212) and an output terminal (OUT). A NMOS transistor (110) is connected between the output terminal and ground. An inverter (120) has an input connected to the output terminal and an output connected to the gate of the NMOS transistor. A diode connects the output terminal to the non-ground voltage terminal (212) to prevent a charge build up on the output terminal when the power is off.

Abstract: To move an article in and out of plasma during plasma processing, the article is rotated by a first drive around a first axis, and the first drive is itself rotated by a second drive, so that the article enters the plasma at different angles for different positions of the first axis. The plasma cross-section at the level at which the plasma contacts the article is such that those points on the article that move at a greater linear velocity (due to being farther from the first axis) move longer distances through the plasma. As a result, the plasma processing time becomes more uniform for different points on the article surface. The direction of rotation of the first and/or second drive changes during processing to improve processing uniformity. The article is allowed to be processed with the plasma only during one-half of each revolution of the second drive.

Abstract: A non-volatile programmable latch (210) has a fuse (F1) connected between a non-ground voltage terminal (212) and an output terminal (OUT). A NMOS transistor (110) is connected between the output terminal and ground. An inverter (120) has an input connected to the output terminal and an output connected to the gate of the NMOS transistor. A diode connects the output terminal to the non-ground voltage terminal (212) to prevent a charge build up on the output terminal when the power is off.

Abstract: A non-volatile programmable latch (210) has a fuse (F1) connected between a non-ground voltage terminal (212) and an output terminal (OUT). A NMOS transistor (110) is connected between the output terminal and ground. An inverter (120) has an input connected to the output terminal and an output connected to the gate of the NMOS transistor. A diode connects the output terminal to the non-ground voltage terminal (212) to prevent a charge build up on the output terminal when the power is off.

Abstract: In a memory system, each data bus is connected to memories connected to different address buses. Each memory allows pipelined read operations such that when data are being read out from a memory in one read operation, the address can be provided to the memory for another read. However, write operations are not pipelined, and the write address and write data are provided to the memory simultaneously. Nevertheless, consecutive reads can overlap with writes. Each write operation uses address and data buses not taken by any read occurring in parallel with the write. The address and data buses are connected to the memories so that no data bus penalty occurs when a memory is switched from a read to a write or from a write to a read. In some embodiments, multiple memories are subdivided into sets of mirror-image memories. In each set, all the memories store the same data.

Abstract: A computer system includes three processors capable to operate concurrently—a scalar processor, a vector processor, and a bitstream processor. In encoding or decoding of video data, the vector processor performs operations that can be efficiently performed by a single instruction multiple data processor, for example, a discrete cosine transform (DCT) and motion compensation. The bitstream processor performs Huffman and RLC encoding or decoding. The bitstream processor can switch contexts to enable the computer system to process several data streams concurrently. The scalar and vector processors can be programmed to execute a single arithmetic or Boolean instruction. The bitstream processor cannot be programmed to execute a single arithmetic or Boolean instruction, but can be programmed to perform an entire video data processing operation. The computer system can handle different video standards. Different Huffman encoding and decoding tables are coded to share memory.

Abstract: In a burst operation, a counter (18) receives one or more bits of a starting column address. The count signal (A[2:1]) generated by the counter is provided to an address adder (20). The address adder generates column address bits (B[2:1]) for a column to be selected in the burst operation. The Y-decoder circuitry (16.0,16.1) selects an even column and an odd column in parallel. The count address bits (A[2:1]) are used as address bits for the even column, and the address bits (B[2:1]) generated by the address adder are used as address bits for the odd column, or vice versa. The even and odd columns can be at non-consecutive column addresses, or they can be at consecutive column addresses starting at an odd column address boundary. Some embodiments are suitable for burst operations defined by standards for synchronous dynamic random access memories. Some embodiments are suitable for double data rate memories.

Abstract: To fabricate back side contact pads that are suitable for use in a vertical integrated circuit, vias are made in the face side of a wafer, and dielectric and contact pad metal are deposited into the vias. Then the wafer back side is etched until the metal is exposed. When the etch exposes the insulator at the via bottoms, the insulator is etched slower than the wafer material (e.g. silicon). Therefore, when the dielectric is etched off and the metal is exposed, the dielectric protrudes down from the wafer back side around the exposed metal contact pads, by about 8 &mgr;m in some embodiments. The protruding dielectric portions improve insulation between the wafer and the contact pads when the contact pads are soldered to an underlying circuit. In some embodiments, before the contact pads are soldered, additional dielectric is grown on the wafer back side without covering the contact pads.

Abstract: In accordance with the present invention, a circuit provides a bias voltage V1 which is substantially insensitive to variations of a power supply voltage powering the circuit. The circuit includes a detector circuit for generating a signal from the power supply voltage and the bias voltage V1, wherein the signal is substantially insensitive to variations in the power supply voltage while being responsive to the bias voltage V1. The circuit further includes a voltage generator circuit for generating the bias voltage V1 wherein the voltage generator is responsive to the signal such that the detector circuit and the voltage generator maintain the bias voltage V1 at a substantially constant value over power supply voltage variations. The detector circuit also includes a circuit for allowing bias voltage V1 to get arbitrarily close to the ground voltage but not allowing the bias voltage V1 to become positive.

Abstract: In a memory system, each data bus is connected to memories connected to different address buses. Each memory allows pipelined read operations such that when data are being read out from a memory in one read operation, the address can be provided to the memory for another read. However, write operations are not pipelined, and the write address and write data are provided to the memory simultaneously. Nevertheless, consecutive reads can overlap with writes. Each write operation uses address and data buses not taken by any read occurring in parallel with the write. The address and data buses are connected to the memories so that no data bus penalty occurs when a memory is switched from a read to a write or from a write to a read. In some embodiments, multiple memories are subdivided into sets of mirror-image memories. In each set, all the memories store the same data.

Abstract: An article holder uses a gas flow, for example, a vortex, to hold the article in a desired position. The gas flow is substantially restricted to an article portion reserved for handling. The result of the processing is less sensitive to the condition (e.g. temperature) of that portion than to the condition of the rest of the article. Therefore, if the gas flow affects the condition (e.g., temperature) of the article portion contacting the gas flow, the processing result is improved.

Abstract: In a bipolar or BiCMOS process, a heavily doped buried layer of a first conductivity type and a heavily doped channel stop region of a second conductivity type are formed in a lightly doped substrate of the second conductivity type. A lightly doped epitaxial layer of the first conductivity type is grown. An implant of the first conductivity type creates a guard ring around the bipolar transistor active region and also creates a higher-doped collector region inside the active region. In the BiCMOS process, during the formation of CMOS wells, a silicon nitride mask over the bipolar transistor inhibits oxidation of the epitaxial layer and the oxidation-enhanced diffusion of the buried layer. As a result, the epitaxial layer can be made thinner, reducing the collector resistance. The MOS transistor wells can be formed without an underlying buried layer, simplifying the process and decoupling the bipolar and MOS transistor characteristics from each other.

Abstract: To exchange data in the same position in the hybrid ring control cycles in two FDDI-II rings, the cycles of the different rings are phase and frequency aligned. To achieve phase alignment, a hybrid multiplexer in one of the rings monitors the cycles on the other ring and starts a cycle when the hybrid multiplexer detects a starting delimiter on the other ring. In order to achieve frequency alignment, 8 KHz references produced by two hybrid multiplexers on the two respective rings are provided to a circuit that selects one of the references to determine the frequency for synchronizing cycle outputs of both hybrid multiplexers.

Abstract: In a BiCMOS process, a gate oxide is grown over the MOS transistors and over the base regions of the bipolar transistors. The base is implanted through the gate oxide and, in some embodiments, through a thin polysilicon layer overlying the base oxide. Then an opening is etched over the base regions in the thin polysilicon layer and the gate oxide, another polysilicon layer is deposited, and the two polysilicon layers are patterned to provide emitter contact regions and gate regions. The polysilicon etch terminates on the gate oxide. After an LDD implant or implants, an insulating layer is deposited and etched anisotropically to create spacers on the sidewalls of the emitter contact regions and the gate regions. During the etch, the gate oxide is etched away around the spacers to expose the extrinsic base regions and the source and drain regions.

Abstract: A bipolar transistor is provided in which the emitters do not traverse the base but terminate inside the top surface of the base. Each emitter is L-shaped in some embodiments. The base top surface has a polygonal or circular outer boundary. The transistor has a long emitter perimeter available for base current flow and more than two emitter sides (e.g., five sides) available for base current flow. Further, the transistor has a large ratio of the emitter area to the base area. Consequently, the transistor has low noise, high gain, high frequency range, and a small size.

Abstract: In a bipolar transistor, the collector and the base are formed in an isolation region laterally bounded by a field insulator. The isolation region corners are spaced far from the emitter to reduce the collector-emitter leakage current. The base does not extend laterally throughout the isolation region. Thus the base is small and the collector-base capacitance is small as a result. Those corners of the isolation region that are not covered by a base contact region are covered and contacted by an insulator. This insulator prevents the field insulator from being pulled back during wafer clean steps. Consequently, the field insulator does not expose the collector. Further, the insulator covering the corners prevents the metal silicide on the surface of the extrinsic base from contacting the corners. The insulator overlying the corners thus reduces the collector-base leakage current.

Abstract: A bipolar transistor is provided in which the base-emitter junctions do not traverse the base but terminate inside the top surface of the base. The transistor has long emitter perimeter available for current flow and more than two emitter sides (e.g., three sides) available for current flow, which allows obtaining a low base resistance, a low emitter resistance, a low collector resistance, a low base-collector capacitance, and a small size.