Abstract: A method for cell placement in an integrated circuit design that uses a calculated diffusion velocity determined from a density value in order to relocate the cells until the cell placement reduces the density below a predetermined threshold. The method acts to control the movement of different cells to reduce the density of the cells prior to legalization of the cell placement.

Abstract: A method and apparatus for an independent operating system that prevents certain classes of computer attacks. Instruction decryption is performed on an existing instruction set for a processor. The processor architecture limits the impact on processor execution timing. The instruction execution timing is not altered in the processor core and any additional processing is overlapped into existing operations.

Abstract: An identification system that may be used in heterogeneous computing environments provides a fail-free path to providing identifiers from a single canonical namespace. Objects or gateways requiring an identifier for access are accessed using an identifier for the canonical namespace. If an entity requests access using an identifier from another namespace, an external database is consulted to determine if a mapping exists for the identifier to another identifier the canonical namespace. If no mapping exists, or the external database is unavailable, then an identifier is automatically generated in the canonical namespace and is used for the access. An internal database is updated with the automatically generated identifier, providing a mechanism to add mappings without administrative intervention. To access resources requiring an identifier from another particular namespace, a canonical namespace identifier may be mapped to another identifier in the particular namespace, or a generic identifier may be used.

Abstract: A method and apparatus for controlling a selectable voltage audio power output stage provides a mechanism for raising the selected power amplifier output voltage in time for the arrival of signal peaks to avoid clipping. Signal peaks may either be delayed by delaying an increase in volume control level or enabling signal compression for a predetermined time period, so that sufficient time is provided for the amplifier power supply to stabilize at a higher operating voltage when an increase of power supply voltage is selected. Alternatively, a signal level may be determined at an upstream source, such as a decoder or filter that provides information in sufficient advance of the arrival of the peaks, and used to control the power supply selection, so that the higher power supply voltage level is selected in advance of arrival of the signal peaks that would otherwise cause clipping at the power amplifier output.

Abstract: A memory provides reduction in access latency for frequently-accessed values by self-organizing to always move a requested value to a front-most central storage element of a spiral. The occupant of the central location is swapped backward, which continues backward through the spiral until an empty location is swapped-to, or the last displaced value is cast out of the last location in the spiral. The elements in the spiral may be cache memories or single elements. The resulting cache memory is self-organizing and for the one-dimensional implementation has a worst-case access time proportional to N, where N is the number of tiles in the spiral. A k-dimensional spiral cache has a worst-case access time proportional to N1/k. Further, a spiral cache system provides a basis for a non-inclusive system of cache memory, which reduces the amount of space and power consumed by a cache memory of a given size.

Abstract: Printed wiring board (PWB) provides for reduction in pin counts required for power plane (including ground plane) connections and/or reduction in requirements for connector current handling per pin. Multiple collinear slots in the form of a dashed line are introduced in the metal layer implementing the power plane that alter the current distribution in the power plane and improve the strength of the PWB. The per-pin current profile for connector pins connected to the power plane is equalized by tuning the length of the slot(s). The slots are dashed and may be made internal to the power plane metal layer to avoid weakening the metal layer for laminated multi-layer PWBs and may be shaped around a connector end when the power plane pin allocation is not uniform at the connector ends. The resulting equalization reduces either pin count required for carrying the power plane current or reduces connector pin current requirements.

Abstract: A network controller improves load-balancing within a network system without requiring an intelligent switch having TCP splicing capability. The network controller forwards connections in response to directives from the connected server, permitting connection splicing within the network controller, but in response to a determination within the server that a connection to an alternative node is more desirable. The server detects that a packet buffer for an original destination node exceeds a threshold and sends a command to the network controlled to forward connections to an alternate destination node. The alternative node connection can be determined based on data availability, server load or other criteria. The packet forwarding mechanism and can be implemented very compactly within the firmware of the network controller and the server forwarding control can be communicated via the network controller device driver.

Abstract: A method, information processing system, and computer readable medium manage a plurality of network interfaces. A data packet is accepted at a pseudo network interface. The pseudo network interface manages a plurality of underlying physical network interfaces. The pseudo network interface selects selected physical network interface from the plurality of physical network interfaces for outputting the data packet. The data packet is modified to include a hardware address associated with the selected physical network interface in response to the selecting. The data packet that has been modified is forwarded to the physical network interface that has been selected.

Abstract: A tile for use in a tiled storage array provides re-organization of values within the tile array without requiring sophisticated global control. The tiles operate to move a requested value to a front-most storage element of the tile array according to a global systolic clock. The previous occupant of the front-most location is moved or swapped backward according to the systolic clock, and the new occupant is moved forward according to the systolic clock, according to the operation of the tiles, while providing for multiple in-flight access requests within the tile array. The placement heuristic that moves the values is determined according to the position of the tiles within the array and the behavior of the tiles. The movement of the values can be performed via only next-neighbor connections of adjacent tiles within the tile array.

Abstract: A resonant switching power converter having burst mode transitioning operates during low or zero load conditions with reduced audible noise and component stresses, while improving efficiency. Pulse bursts are generated with a beginning and/or ending pulse duration that differs from mid-burst pulse durations, in order to reduce an amplitude of transients otherwise generated at the beginning and/or end of the bursts. Alternatively, the spacing between the pulses at the beginning and/or end of the bursts may differ from the spacing between the pulses in the middle of the bursts to reduce the transient(s). A number of pulses at the beginning and/or end of the burst can also be set with gradually varying durations, to further reduce component stress and audible vibration in a transformer that couples the resonant tank to the output of the converter.

Abstract: A hysteretic buck converter provides improved regulation control, in particular for buck converter standby operation. A comparison circuit compares the output voltage of the buck converter to a waveform that is generated from an indication of the output current of the converter, so that the turn-on time of the converter is advanced as the output current demand increases. The resulting action anticipates a reduction in output voltage due to the increased current, preventing an excursion of the output voltage below the ripple voltage minimum. The turn-off time of the converter is controlled by an upper threshold that limits the ripple voltage maximum. The output current indication may be a measurement of output current, or may be a dynamic value calculated from the input voltage and the output voltage waveform.

Abstract: A delta-sigma analog-to-digital converter (ADC) circuit improves performance by reducing the amount of noise and other error sampled by the reference switching circuit. The reference is operated such that one or more reference capacitors remain coupled to an input summing node of the ADC input integrator when an input value to a feedback digital-to-analog converter (DAC) indicates that their contribution is not required to apply a reference in the next quantization period. The reference switching network can select from two or more of the following reference options: 1) switch the reference capacitor to apply a charge quanta as per an ordinary switched-capacitor cycle, 2) switch the reference voltage on a second terminal of the reference capacitor to apply an opposite polarity charge quanta, or 3) leave the first terminal of the reference capacitor coupled to the integrator without changing the voltage at the second terminal of the reference capacitor.

Abstract: A boosted auxiliary winding power supply for a switched-power converter circuit provides operating voltage for control and other circuits early in the start-up phase of converter operation. A boost circuit has an input coupled to the auxiliary winding to boost the voltage available from the auxiliary winding at least during start-up of the switched-power converter. The boost thereby provides a voltage that is greater than the voltage across the auxiliary winding during start-up of the switched-power converter. The boost circuit may be actively switched at a rate higher than a switching rate of the switched-power converter, to increase a rate of rise of the operating voltage. Polarity information, which may be provided from the switched-power converter control circuit, can be used to actively rectify the output of the auxiliary winding.

Abstract: A method and system for decreasing power consumption in memory arrays having usage-driven power management provides decreased power consumption in the memory array of a processing system. Per-page usage information is gathered on memory by a memory controller and periodically evaluated by software. The software distinguishes between more frequently accessed pages and less frequently accessed pages by analyzing the gathered usage information and periodically migrates physical memory pages in order to group less frequently accessed pages and more frequently access pages in separately power-managed memory ranks. When used in conjunction with a usage-driven power management mechanism, the ranks containing the less frequently accessed pages can enter deeper power-saving states and/or any power-saving state for longer periods.

Abstract: A digital transmission circuit and interface provide selectable power consumption via multiple weighted driver slices, improving the flexibility of an interface while reducing transmitter power consumption, area and complexity when possible. A cascaded series of driver stages is provided by a set of parallel slices and a control logic that activates one or more of the slices, which combine to produce a cascaded active driver circuit. The power consumption/drive level selectability of the slice combination provides a driver that can be fine-tuned to particular applications to provide the required performance at a minimum power consumption level.

Abstract: An efficient method and computer program for modeling and improving stating memory performance across process variations and environmental conditions provides a mechanism for raising the performance of memory arrays beyond present levels/yields. Statistical (Monte-Carlo) analyses of subsets of circuit parameters are performed for each of several memory performance variables and then sensitivities of each performance variable to each of the circuit parameters are determined. The memory cell design parameters and/or operating conditions of the memory cells are then adjusted in conformity with the sensitivities, resulting in improved memory yield and/or performance. Once a performance level is attained, the sensitivities can then be used to alter the probability distributions of the performance variables to achieve a higher yield.

Abstract: A method and computer program product for controlling a storage device using per-element selectable power supply voltages provides energy conservation in storage devices while maintaining a particular performance level. The storage device is partitioned into multiple elements, which may be sub-arrays, rows, columns or individual storage cells. Each element has a corresponding virtual power supply rail that is provided with a selectable power supply voltage. The power supply voltage provided to the virtual power supply rail for an element is set to the minimum power supply voltage unless a higher power supply voltage is required for the element to meet performance requirements. A control cell may be provided within each element that provides a control signal that selects the power supply voltage supplied to the corresponding virtual power supply rail. The state of the cell may be set via a fuse or mask, or values may be loaded into the control cells at initialization of the storage device.

Abstract: A method for automatically initializing the operational settings of a system from information stored within a non-volatile storage of an integrated circuit so that the operational requirements of the integrated circuit, which may be a microprocessor, are met by the system when the system is operating. During manufacturing test, environmental requirements of the integrated circuit are determined and stored within the non-volatile storage of the integrated circuit. During system initialization, environmental control values such as required operating voltage and frequency and cooling requirements are determined from the test values, which are read from the integrated circuit. The values are read by an interface of the system from an interface of the integrated circuit. System settings are controlled by the values to provide the required operating environment and the values may be captured within the system for subsequent operations and initialization sequences.

Abstract: A method and system for managing peripheral connection wakeup signaling in a processing system supporting multiple virtual machines provides a mechanism by which ownership of a peripheral having system wakeup capability is transferred between virtual machines. The power management event signal is connected to a service processor input that in turn signals a hypervisor to direct the wakeup activity to a particular logical partition in which the virtual machine was last executing. The hypervisor can then determine whether or not to wake up the entire system, or portions thereof and can direct the power management event to the appropriate virtual machine. In particular the peripheral may be an Ethernet adapter supporting Wake-On-LAN capability. State initialization, which is typically ensured by system power cycling is provided instead by controlling power to the standby power source or in some instances by forcing an indication of a disconnect/reconnect of the wakeup signaling connection.

Abstract: A method, system and computer program product for filtering systematic differences from wafer evaluation parameters provides an efficient visual display and numerical map technique for observing wafer-level process variation. Measurement data is gathered from electronic circuits at multiple positions within multiple regions on one or more wafers and parameters are computed from the measurement data, which may be the measurement data values themselves. The set of parameters is filtered for expected systematic variation by computing a set of normalization values from the set of parameters and normalizing the data according to the normalization values. The normalized parameter set is then either presented in a visual display, e.g., by color mapping, or arranged in a numerical map of parameter value by location.