Abstract: A modulated amplifier output enable control eliminates audible pops when enabling and disabling an audio amplifier output stage. The output of the audio amplifier is transitioned between an enabled state and a disabled state using a modulated control signal that enables and disables the output of the audio amplifier. Durations of the enabled state vs. the disabled state of the amplifier are adjusted to cause a transition between a fully disabled state and a fully enabled state of the audio amplifier so that the transition between the disabled state and the enabled state of the amplifier output is inaudible.

Abstract: A technique for performing stream detection and prefetching within a cache memory simplifies stream detection and prefetching. A bit in a cache directory or cache entry indicates that a cache line has not been accessed since being prefetched and another bit indicates the direction of a stream associated with the cache line. A next cache line is prefetched when a previously prefetched cache line is accessed, so that the cache always attempts to prefetch one cache line ahead of accesses, in the direction of a detected stream. Stream detection is performed in response to load misses tracked in the load miss queue (LMQ). The LMQ stores an offset indicating a first miss at the offset within a cache line. A next miss to the line sets a direction bit based on the difference between the first and second offsets and causes prefetch of the next line for the stream.

Abstract: A method, test circuit and test system provide measurements to accurately characterize threshold voltage changes due to negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI). Both the bias temperature instability recovery profile and/or the bias temperature shifts due to rapid repetitions of stress application can be studied. In order to provide accurate measurements when stresses are applied at intervals on the order of tens of nanoseconds while avoiding unwanted recovery, and/or to achieve recovery profile sampling resolutions in the nanosecond range, multiple delay or ring oscillator frequency measurements are made using a delay line that is formed from delay elements that have delay variation substantially caused only by NBTI or PBTI effects. Devices in the delay elements are stressed, and then the delay line/ring oscillator is operated to measure a threshold voltage change for one or more measurement periods on the order of nanoseconds.

Abstract: A system and circuit for determining data signal jitter via asynchronous sampling provides a low cost and production-integrable mechanism for measuring data signal jitter. The data signal is edge-detected and sampled by a sampling clock of unrelated frequency the sampled values are collected in a histogram according to a folding of the samples around a timebase. The timebase is determined by sweeping to detect a minimum jitter for the folded data. The histogram for the correct estimated timebase period is representative of the probability density function of the location of data signal edges and the jitter characteristics are determined by the width and shape of the density function peaks. Frequency drift can be corrected by adjusting the timebase used to fold the data across the sample set.

Abstract: A method and system for estimating processor utilization from power measurements provides an estimate of processor utilization that can be computed outside of the processor and operating system. Measurements of the processor power consumption are gathered over short intervals in a histogram. The idle power consumption of the processor is determined, and a threshold value higher than the idle power consumption level is computed from the idle power consumption. The number of histogram counts for bins greater than the threshold is normalized to the total number of measurements, providing a fractional value that corresponds to the processor utilization over the measurement interval. The fractional value can then be used in a power management algorithm that adjusts the frequency and optionally the voltage of the processor or group of processors based on their utilization.

Abstract: A test system and computer program for measuring threshold voltage variation using a device array provides accurate threshold voltage distribution values for process verification and improvement. The test system and computer program control a characterization array circuit that imposes a fixed drain-source voltage and a constant channel current at individual devices within the array. Another circuit senses the source voltage of the individual device within the array. The statistical distribution of the threshold voltage is determined directly from the source voltage distribution by offsetting each source voltage by a value determined by completely characterizing one or more devices within the array. The resulting methodology avoids the necessity of otherwise characterizing each device within the array, thus reducing measurement time dramatically.

Abstract: Routing between multiple hosts and adapters in a PCI environment is provided by a method and system. A Destination Identification (DID) field is inserted in a field of the PCI bus address (PBA) of transaction packets dispatched through PCI switches. A particular DID is associated with a particular host or system image, and thus identifies the physical or virtual end point of the packets. The method and system may track connections such that when particular host of a root node becomes connected to a specified switch, a PCI Configuration Master (PCM), residing in one of the root nodes, is operated to enter a destination identifier or DID into a table. The DID is then inserted in the PBA of packets directed through the specified switch from the particular host to one of the adapters.

Abstract: A delta-sigma analog-to-digital converter (ADC) having a serialized quantizer output has a data rate greater than a quantization rate of the delta-sigma modulator, but less than a bit rate determined by the product of the number of bits required to represent the input to a feedback digital-to-analog converter and the quantization rate. Additional information can be encoded in the serial bit stream by selection among redundant codes based on the value of the additional information. The serial bit stream may encode differences between successive quantizer output samples and the additional information may include the absolute value of the quantizer output, synchronization information and/or framing information for distinguishing data corresponding to multiple ADC input channels.

Abstract: A method and logical apparatus for managing processing system resource use for speculative execution reduces the power and performance burden associated with inefficient speculative execution of program instructions. A measure of the efficiency of speculative execution is used to reduce resources allocated to a thread while the speculation efficiency is low. The resource control applied may be the number of instruction fetches allocated to the thread or the number of execution time slices. Alternatively, or in combination, the size of a prefetch instruction storage allocated to the thread may be limited. The control condition may be comparison of the number of correct or incorrect speculations to a threshold, comparison of the number of correct to incorrect speculations, or a more complex evaluator such as the size of a ratio of incorrect to total speculations.

Abstract: A predication technique for out-of-order instruction processing provides efficient out-of-order execution with low hardware overhead. A special op-code demarks unified regions of program code that contain predicated instructions that depend on the resolution of a condition. Field(s) or operand(s) associated with the special op-code indicate the number of instructions that follow the op-code and also contain an indication of the association of each instruction with its corresponding conditional path. Each conditional register write in a region has a corresponding register write for each conditional path, with additional register writes inserted by the compiler if symmetry is not already present, forming a coupled set of register writes. Therefore, a unified instruction stream can be decoded and dispatched with the register writes all associated with the same re-name resource, and the conditional register write is resolved by executing the particular instruction specified by the resolved condition.

Abstract: A static pulse bus circuit and method having dynamic power supply rail selection reduces static and dynamic power consumption over that of static pulse bus designs with fixed power supply rail voltages. Every other (even) bus repeater is operated with a selectable power supply rail voltage that is selected in conformity with a state of the input signal of the bus repeater. The odd bus repeaters are operated from the lower of the selectable power supply voltages supplied to the even repeaters. The odd bus repeaters may also be operated from a selectable power supply rail voltage opposite the selectable-voltage power supply rail provided to the even bus repeaters, in which case the opposing rail of the even bus repeaters is set to the higher of the voltages selectable in the odd bus repeaters.

Abstract: A computer program for balancing power plane pin currents in a printed wiring board (PWB) provides for reduction in pin counts required for power plane (including ground plane) connections and/or reduction in requirements for connector current handling per pin. One or more slots is introduced in the metal layer implementing the power plane that alter the current distribution in the power plane. The per-pin current profile for connector pins connected to the power plane is equalized by tuning the length of the slot(s). The slots may be dashed or made internal to the power plane metal layer to avoid weakening the metal layer for laminated multi-layer PWBs and may be shaped around a connector end when the power plane pin allocation is not uniform at the connector ends. The resulting equalization reduces either pin count required for carrying the power plane current or reduces connector pin current requirements.

Abstract: A method and system and calibration technique for power measurement and management over multiple time frames provides responsive power control while meeting global system power consumption and power dissipation limits. Power output of one or more system power supplies is measured and processed to produce power values over multiple differing time frames. The measurements from the differing time frames are used to determine whether or not system power consumption should be adjusted and then one or more devices is power-managed in response to the determination. The determination may compare a set of maximum and/or minimum thresholds to each of the measurements from the differing time frames. A calibration technique uses a precision reference resistor and voltage reference controlled current source to introduce a voltage drop from the input side of a power supply sense resistor calibration is made at the common mode voltage of the power supply output.

Abstract: A method and test circuit provide measurements to aid in the understanding of time-varying threshold voltage changes such as negative bias temperature instability and positive bias temperature instability. In order to provide accurate measurements during an early stage in the threshold variation, a current generating circuit is integrated on a substrate with the device under test, which may be a device selected from among an array of devices. The current generating circuit may be a current mirror that responds to an externally-supplied current provided by a test system. A voltage source circuit may be included to hold the drain-source voltage of the transistor constant, although not required. A stress is applied prior to the measurement phase, which may include a controllable relaxation period after the stress is removed.

Abstract: A circuit substrate uses post-fed top side power supply connections to provide improved routing flexibility and lower power supply voltage drop/power loss. Plated-through holes are used near the outside edges of the substrate to provide power supply connections to the top metal layers of the substrate adjacent to the die, which act as power supply planes. Pins are inserted through the plated-through holes to further lower the resistance of the power supply path(s). The bottom ends of the pins may extend past the bottom of the substrate to provide solderable interconnects for the power supply connections, or the bottom ends of the pins may be soldered to “jog” circuit patterns on a bottom metal layer of the substrate which connect the pins to one or more power supply terminals of an integrated circuit package including the substrate.

Abstract: An auto routing method and system provides optimized circuit routing while maintaining proper reference return paths for critical signals. Critical signal paths are auto-routed simultaneously with corresponding reference return paths, and the reference return paths can be merged into reference planes if they are adjacent to regions connected to the same reference net. The reference return paths may be in a plane adjacent to the signal path plane in the same channel, or the reference returns may be routed in adjacent channels in the same plane as the signal path. A check may be performed on endpoints of each critical signal path to determine whether a reference return via is present within a proximity tolerance of the signal path endpoints, and a reference return via placed if not.

Abstract: A computer implemented method and apparatus are provided for transferring data in a logical partitioned data processing system. A receiving adapter receives data from a network. The receiving adapter transfers the data to a pre-mapped buffer if the data is to be sent to a target adapter. A virtual bridge receives the pre-mapped buffer from the receiving adapter and transfers the pre-mapped buffer to the target adapter. The target adapter receives the pre-mapped buffer from the virtual bridge and determines that the received buffer is pre-mapped. The target adapter accesses the pre-mapped buffer using pre-mapped mapping, and transmits the data contained therein.

Abstract: A charge pump power supply for a consumer device audio power stage has an efficiency selected according to signal level. The frequency of operation of the charge pump and/or the effective size of a switching transistor bank is adjusted based upon a volume (gain) setting, or a detected signal level, so that internal power consumption of the charge pump is reduced when high output current is not required from the audio power stage and consequently from the charge pump. Operating modes of the charge pump are selected by the signal level indication and include at least a high power and a high efficiency mode selected by setting the charge pump operating frequency and/or enabling or disabling switching of one or more of multiple parallel transistors used to implement each switching element of the charge pump, thereby setting the level of gate capacitance being charged/discharged by the gate driver circuit(s).

Abstract: Each instruction thread in a SMT processor is associated with a software assigned base input processing priority. Unless some predefined event or circumstance occurs with an instruction being processed or to be processed, the base input processing priorities of the respective threads are used to determine the interleave frequency between the threads according to some instruction interleave rule. However, upon the occurrence of some predefined event or circumstance in the processor related to a particular instruction thread, the base input processing priority of one or more instruction threads is adjusted to produce one more adjusted priority values. The instruction interleave rule is then enforced according to the adjusted priority value or values together with any base input processing priority values that have not been subject to adjustment.

Abstract: A digital output semiconductor magnetic field sensor integrated circuit provides a low-cost and dense packaging solution for providing digital indicators of magnetic field magnitudes. A delta-sigma modulator based analog-to-digital converter (ADC) is integrated on a die with a semiconductor magnetic field sensor. The delta-sigma modulator provides for noise-shaping the sensor output and the co-location of the sensor and the converter on the die provides for improved noise immunity. The current loops of the ADC and digital interface are made as small as possible and are disposed on the die so that they are orthogonal to the axis of the magnetic field sensor, so that noise from the converter operation is isolated from the sensor.