Abstract: Net routing is optimized in an integrated circuit device by dividing an integrated circuit design with a first group of substantially parallel lines in a first direction and with a group of substantially parallel lines in a second direction, with the second direction being substantially perpendicular to the first direction. A first routing graph is formed with vertices corresponding to locations where lines in the first direction and lines in the second direction cross, and nets are globally routed as a function of the first routing graph. The integrated circuit design is further subdivided with a second group of substantially parallel lines in the first direction, and a second routing graph is formed with vertices corresponding to locations where lines in the first and second groups of substantially parallel lines in the first direction cross lines in the group of substantially parallel lines in the second direction.

Abstract: The present invention is a method and apparatus for applying one-dimensional proximity correction to a piece of a mask pattern, by segmenting a first piece of a mask pattern with horizontal dividing lines into a plurality of segments, segmenting a second piece of said mask pattern with said horizontal dividing lines into a second plurality of segments, and applying proximity correction to a first segment from said first plurality of segments taking into consideration a second segment from said second plurality of segments.

Abstract: Routing of electrical connections between cells arranged in cell columns on an integrated circuit (IC) die. Electrical connections are routed on a routing layer between cells located in a first cell column. An identification is made of an available off-grid resource capable of being used for wire routing that is both within the first cell column and on the routing layer. An electrical connection is routed between a first cell and a second cell located in different cell columns using at least a portion of the identified available off-grid resource. Also, an integrated circuit die which includes vertical power rails and vertical ground rails. Cell columns, including a first cell column and a second cell column, are each bordered by a vertical power rail and a vertical ground rail. A channel is provided between the first cell column and the second cell column.

Abstract: A method of synthesizing integrated circuit chip (IC) designs having clock signals defined internal to a module comprising the steps of mapping the IC design to a target technology with the internal clock defined, removing definitions of the internal clock, re-synthesizing the IC design, and re-defining the internal clock using new names of clock sources.

Abstract: A method and system for preventing information losses during alternative frequency searches by a receiving unit in a communication system in which data is channel coded, interleaved, and segmented into a plurality of frames. The method comprises the steps of discontinuing demodulation at a predetermined time before a frame ends, inserting zero values into the frame, and performing a search for alternative frequencies while continuing to insert zero values into the frame and then a next frame. After the search is completed, insertion of zero values is discontinued and demodulation is resumed. In one preferred version, the receiving unit comprises a mobile radio station operating at a serving frequency. The step of inserting zero values is followed by a step of programming the mobile radio station to a search frequency and waiting for the mobile radio station to settle.

Abstract: A large number of possible cell placements for an integrated circuit chip are evaluated to determine which has the highest fitness in accordance with a predetermined criteria such as interconnect congestion. Each cell placement, which constitutes an individual permutation of cells from a population of possible permutations, is represented as an initial cell placement in combination with a list of individual cell transpositions or swaps by which the cell placement can be derived from the initial cell placement. A cell placement can be genetically mutated and/or inverted by adding swaps to the list for its cell placement which designates cells to be transposed. Genetic crossover can be performed by transposing swaps between the lists for two cell placements. This cell representation and transposition method enables any type of cell transposition to be performed without loss or duplication of cells or generation of illegal placements.

Abstract: An object of the present invention is to provide for a method and apparatus to partition high fanout nets into smaller subnets. Said method includes the steps of identifying elementary pairs of pins in the net, each such elementary pair defining a line; eliminating lines such that a planar graph is formed; eliminating further lines such that a spanning tree is formed, said spanning tree connecting each pin in the net; identifying basic elements, each basic element forming a portion of said spanning tree; and constructing a connected cover for said net, said connected cover comprising a plurality of said basic elements.

Abstract: A system which enables a user to preview a document by providing a user interface and inputting, via the user interface, information specifying an arrangement of components to create the document, the components including at least two of: a printed page, a tab page, a blank page, a front cover, a back cover, and a binding. Digital images of at least some of the components specified by the input information are obtained and an image of the document is generated by combining the digital images of at least some of the components in a manner so as to simulate an appearance of the document were the document to be physically assembled according to the input information. The image of the document is then caused to be displayed.

Abstract: Integrated circuit chips (IC's) require proper placement of many cells (groups of circuit components) and complex routing of wires to connect the pins of the cells. Because of the large number of the cells and the complex connections required, it is essential that placement of the cell and the wire routine be done correctly to avoid any congestion of wires. Placement of the cells and the routing of the wires to avoid congestion can be accomplished by determining congestion of various regions, or pieces, of the IC's after an initial placement of the cells and routing of the wires. The present invention discloses a method and apparatus to define the regions, or pieces, of the IC, determine various density measurement of the pieces, and adjust the sizes of the pieces to reduce congestion of congested pieces by reallocating space from uncongested pieces to congested pieces.

Abstract: Integrated circuit chips (IC's) require proper placement of many cells (groups of circuit components) and complex routing of wires to connect the cells. Designing of the IC's require meeting real-world constraints one of which is the performance of the IC, or the period of time required by the integrated circuit to produce the output signals from the time the input signals are available. Typically, the performance of an integrated circuit is determined by the slowest path of the signals, called the critical path. The critical path is usually only a small portion of the IC. The present invention discloses a method and apparatus for transforming the circuits comprising the critical path, thereby increasing the performance of the entire IC. The transformation is performed by segmenting, or blocking, the cells which make up the critical path. Then, each block is transformed, or replaced, with a resynthesized circuit to which both the digital 0 and digital 1 values are provided.

Abstract: Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclosed. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons, by triangles, by parallelograms, and by other polygons enabling a variety of cell shapes to be accommodated. Polydirectional non-orthogonal three layer metal routing is disclosed. The architecture may be combined with the tri-directional routing for a particularly advantageous design. In the tri-directional routing arraingement, electrical conductors for interconnecting terminals of microelectronic cells of an integrated circuit preferrably extend in three directions that are angularly displaced from each other by 60.degree.. The conductors that extend in the three directions are preferrably formed in three different layers. A method of minimizing wire length in a semiconductor device is disclosed. A method of minimizing intermetal capacitance in a semiconductor device is disclosed.

Abstract: When a mobile communication unit (e.g. a cellular telephone) is powered up, the unit must lock on to a local base station, or "acquire" a base station signal, to enable the user to send and receive calls. To lock on a local base station, the mobile unit must determine the delay at which the base station is sending the pseudo random (PN) code. This process is called the "acquisition." The current art of acquiring a base station involves collecting a set of samples at a particular code phase, or delay, testing the collected sample, and repeating these steps using another code phase until the correct code phase is found. The present invention discloses a method and apparatus for collecting a set of samples at a particular code phase, and simultaneously testing the collected sample and collecting the next set of samples for another code phase.

Abstract: The present invention concerns a high resolution calibrator for a sleep mode clock of a mobile station in a wireless communications system. When the mobile station is in idle mode (i.e., listening to a paging channel periodically, but otherwise taking no action), the control processor commands the mobile station to enter into sleep mode to minimize power consumption. During sleep mode, the high-frequency reference clock and circuitry clocked by it are turned off. Only the calibrated low-frequency clock remains operating to clock the sleep logic. In a preferred version, the calibrator includes two counters: a first counter which counts up to S*T0 cycles of the super chip rate clock through one data frame, then rolls over to zero, and a second counter which counts cycles of the sleep mode clock.

Abstract: A method of cell placement for an integrated circuit chip includes performing a contraction operation by which at least some of the cells are relocated to new positions that provide lower interconnect wirelength. For each cell, the centroid of the net of cells to which the cell is connected is computed. The cell is then moved toward the centroid by a distance that is equal to the distance from the current position of the cell to the centroid multiplied by a "chaos" factor. This process continues until a specific energy condition is met; then the `expansion` mode is entered. An expansion operation is then performed by which the net force exerted on each cell by other cells in the placement and a resulting altered velocity of the cell are calculated, and a new cell position is calculated based on the altered velocity over an incremental length of time. The system stays in expansion mode until another energy criterion is met.

Abstract: Integrated circuit chips (IC's) require proper placement of many cells (groups of circuit components) and complex routing of wires to connect the pins of the cells. Because of the large number of the cells and the complex connections required, it is essential that placement of the cell and the wire routine be done correctly to avoid any congestion of wires. The present invention discloses method and apparatus to optimize the cell density of the segments of columns on the IC. To optimize the segment or column density, the present columns densities are calculated, and the desired densities are determined. Then, the amount and the location of the of cell overload is found. The cells of the overloaded columns are spread out the neighboring columns. The reassignment of the cells are performed to minimize the distance, therefore the affect, of the relocation.

Abstract: Integrated circuit chips (IC's) require proper placement of many cells (groups of circuit components) and complex routing of wires to connect the pins of the cells. Because of the large number of the cells and the complex connections required, it is essential that placement of the cell and the wire routine be done correctly to avoid any congestion of wires. The present invention discloses method and apparatus to reduce or to eliminate cell placement and wire routing congestion. The congestion reduction is achieved by first examining regions of the IC to determine whether horizontal or vertical congestion exists. If horizontal congestion exists, then the cells are moved, within the columns, vertically to give more room for the cells and in between the cells for the routing of the wires. If vertical congestion exists, then the cells are moved to different columns to alleviate congestion.

Abstract: A system for determining an affinity associated with relocating a cell located on a surface of a semiconductor chip to a different location on the surface is disclosed herein. Each cell may be part of a cell net containing multiple cells. The system initially defines a bounding box containing all cells in the net which contains the cell. The system then establishes a penalty vector based on the bounding box and borders of a region containing the cell, computes a normalized sum of penalties for all nets having the cell as a member, and calculates the affinity based on the normalized sum of penalties. Also included in the disclosed system are methods and apparatus for capacity and utilization planning of the use of the floor, or the surface area, and the methods and apparatus for parallelizing the process of affinity based placements using multiple processors. Finally, method and apparatus for connecting the cells based on a Steiner Tree method is disclosed.

Abstract: When a mobile communication unit (e.g. a cellular telephone) is powered up, the unit must lock on to a local base station, or "acquire" a base station signal, to enable the user to send and receive calls. To lock on a local base station, the mobile unit must determine the delay at which the base station is sending the pseudo random (PN) code. This process is called the "acquisition." The current art of acquiring a base station involves searching the possible code phases, or delays, one by one until the first signal is found. However, multiple base stations may be available to the mobile user, and the first found pilot signal may not be the strongest and may not be from the nearest base station. The present invention discloses a method and apparatus for searching all possible PN code phases and selecting the strongest phase instead of selecting the first phase.

Abstract: A method for laying out input/output (I/O) pairs, each including an I/O cell and a pad, on an integrated circuit die. Size information is obtained for each of a first I/O pair and a second I/O pair. A minimum pad spacing criterion is obtained which specifies a minimum distance between the pad in the first I/O pair and an element of the second I/O pair, and the first I/O pair and the second I/O pair are laid out so as to satisfy the minimum pad spacing criterion. Also provided is a method for laying out pads for input/output (I/O) cells on an integrated circuit die in which size information is obtained for each of a first I/O cell pad and a second I/O cell pad. A minimum pad spacing criterion is obtained, and the first I/O cell pad and the second I/O cell pad are laid out so as to satisfy the minimum pad spacing criterion.

Abstract: Integrated circuit chips (IC's) require proper placement of many cells (groups of circuit components) and complex routing of wires to connect the pins of the cells. Because of the large number of the cells and the complex connections required, it is essential that placement of the cell and the wire routine be done correctly to avoid any congestion of wires. The present invention discloses method and apparatus to reduce or to eliminate cell placement and wire routing congestion. To reduce vertical congestion, the cells are moved from congested regions to uncongested regions. The present invention discloses techniques of defining regions as pieces and columns, determining the level of congestion in the regions, and the methods of moving the cells to different columns to reduce congestion while minimizing affects to wire routing. The movement of the cells to other columns may create overlapping of the cells or overloading of the columns.