Abstract: The present invention discloses an apparatus for removing unwanted plants from a specific area of soil. The invention is comprised of a blade that is adapted to penetrate the surface of the soil and moving substantially parallel to the surface thereof. Proper movement of the blade is assisted by fins positioned on the sides of the blade, and act similarly to the rudder of a boat. The blade has a support member that has one end attached to the blade and the other end is capable of receiving a handle. The handle is configured in an arcuate shape to better facilitate grasping and holding by the user. This combination allows the user to grasp the handle, one hand on each side of the support member and blade, and push the invention forward undercutting the undesirable plant roots, thereby killing them. Minimal disruption of the soil is experienced, thereby optimizing the efficiency of work done by the user.

Abstract: A cell placement for an integrated circuit chip is divided into two "chessboard" patterns or "jiggles". Each pattern resembles a chessboard in that it consists of alternating regions of different types or "colors" such that no region of a given color has an edge common with another region of the same color. The jiggles are offset relative to each other such that the regions of one jiggle partially overlap at least two regions of the other jiggle. A placement improvement operation such as simulated annealing is performed sequentially for each color of each jiggle. During each operation, a plurality of parallel processors operate on the regions simultaneously using a previous copy of the entire chip, with one processor being assigned to one or more regions. At the end of each operation, the copy of the chip is updated. The chessboard patterns eliminate unproductive cell moves resulting from adjacent regions having a common edge.

Abstract: A system for proportionally partitioning multiple groups of cells on the surface of a semiconductor chip into subregions is disclosed herein. The cell groups are separated by dividing lines, and the system comprising a calculator which determines an offset of the cut line from the dividing line; a shifter which moves the location of said groups of cells by the offset such that the cut line coincides with the dividing line; and an overflow evaluator and compensator which shifts any cells outside said region to an edge of said region.

Abstract: A analog-to-digital conversion apparatus and method for mobile communication devices are disclosed by the present invention. Because the conventional CMOS process does not allow for high order anti-aliasing circuits to be fabricated with digital circuits on the same chip, a new apparatus had to be developed to use low order anti-aliasing filters for the analog-to-digital conversion. The apparatus of the present invention includes a low order anti-aliasing circuit, a delta-sigma converter, and post-conversion filters. The post conversion filters include a decimation circuit, a droop correction filter, and an offset adjust circuit. In this implementation, a low order analog anti-aliasing filter can be used along with a delta-sigma converter and post-conversion filters to eliminate the need for high order analog anti-aliasing filters. Another aspect of the present invention is the duplication of the circuits to process the incoming signals. The duplicate circuit is fed a null signal to process the noise only.

Abstract: A microelectronic integrated circuit includes a semiconductor substrate, and a plurality of CMOS microelectronic devices formed on the substrate. Each device includes a hexagonal ANY element of a first conductivity type (PMOS or NMOS), and a hexagonal ALL element of a second conductivity type (NMOS or PMOS), the ANY and ALL elements each having a plurality of inputs and an output that are electrically interconnected respectively. The ANY element is basically an OR element, and the ALL element is basically an AND element. However, the power supply connections and the selection of conductivity type (NMOS or PMOS) for the ANY and ALL elements can be varied to provide the device as having a desired NAND, AND, NOR or OR configuration, in which the ANY element acts as a pull-up and the ALL element acts as a pull-down, or vice-versa.

Abstract: Integrated circuit chips (IC's) require proper placement of many cells (groups of circuit components) and complex routing of wires to connect the pins of the cells. Designing of the IC's require meeting real-world constraints such as minimization of the circuit area, minimization of wire length within the circuit, and minimization of the time the IC requires to perform its function, referred to as the IC delay. Because of the large number of cells and nets of an IC, the process of determining IC delay of an IC design requires a lot of time. The present invention discloses a method and apparatus for determining the IC delay quickly by using multiple processors and analyzing multiple pins simultaneously. Also disclosed is the method of ordering the pins to allow the application of the parallel processing technique.

Abstract: A novel device for pole splitting which can be employed in multistage amplifiers having a final stage and a prior stage. The device comprises a first capacitor connected between the output of the prior stage and the output of the final stage, a source follower, and a second capacitor connected between the output of the prior stage and the source follower. The source follower provides an offset voltage that reduces variation of the total capacitance of the first and second capacitors. In a preferred version of the present invention, the first and second capacitor each comprise a MOSFET transistor having a certain threshold voltage. The offset voltage is set to be at least the threshold voltage of the MOSFET transistors. In a preferred version, the source follower comprises a plurality of MOSFET transistors, which includes a MOSFET transistor having a gate connected to the first capacitor and a source connected to the second capacitor.

Abstract: A novel method for PN sequence hopping where a PN sequence generator has been disabled for a predetermined time before a future time slot where the PN sequence generator will be enabled. The method comprises the steps of writing a base state into storage for a first hop only, calculating from the base state a new state advancing a PN sequence to the beginning of the future time slot, loading the new state into the PN sequence generator, and enabling the PN sequence generator. For subsequent hops, the base state is the new state calculated in the previous hop. In a preferred version, the step of calculating a new state comprises multiplying the base state by a Galois Field polynomial; a serial Galois Field multiplier can be used to perform this multiplication. A system embodying the present invention comprises a PN sequence generator, a control processor, and a storage device.

Abstract: A multithreaded wavefront routing system for simultaneously planning routes for wiring a semiconductor chip surface. The surface has a plurality of grids located thereon, and routes are planned according to a predetermined netlist. The system steps across the surface from a first location to a second location in a wave-type pattern. The system sequentially steps through the grid arrangement on the chip surface and plans routing one grid at a time using a plurality of threaded processors. The system recognizes pins as it steps through grids and determines a plan for the current grid by evaluating current wire position, target pin location, and any currently planned routes, designating reserved locations wherein the route may be planned subsequent to the current grid, and establishing a wire direction for each wire traversing the current grid.

Abstract: A novel signal processing scheme comprises a digital to analog converter which is clocked at a first frequency, and a switched capacitor filter which receives input from the digital to analog converter and is clocked at a second frequency which is a multiple N times the first frequency. A preferred version of the present invention further comprises an analog signal sychronization circuit which allows the switched capacitor filter to oversample output from the digital to analog converter. The analog signal sychronization circuit comprises a sample and hold circuit, which receives input from the digital to analog converter and holds the input so that the switched capacitor filter can sample the same input N times, and a digital clock generator, which clocks the sample and hold circuit such that the sample and hold circuit only samples settled and valid output data from the digital to analog converter.

Abstract: The present invention is a piano-style attachment apparatus for a computer keyboard comprising a base, a plurality of piano-styled keys hinged to said base, and anchors for anchoring the apparatus over the computer keyboard. Each piano-styled key has a protrusion extending downwardly for striking a corresponding computer key. The anchors comprise walls which extend deep in between computer keys in order to secure the apparatus to the computer keyboard.

Abstract: Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclosed. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons, by triangles, by parallelograms, and by other polygons enabling a variety of cell shapes to be accommodated. Polydirectional non-orthogonal three layer metal routing is disclosed. The architecture may be combined with the tri-directional routing for a particularly advantageous design. In the tri-directional routing arraingement, electrical conductors for interconnecting terminals of microelectronic cells of an integrated circuit preferrably extend in three directions that are angularly displaced from each other by 60.degree.. The conductors that extend in the three directions are preferrably formed in three different layers. A method of minimizing wire length in a semiconductor device is disclosed. A method of minimizing intermetal capacitance in a semiconductor device is disclosed.

Abstract: The capacity of a cache memory is substantially reduced over that required for a multi-chip distributed shared memory (DSM) implementation to enable the cache memory, a main memory, a processor and requisite logic and control circuitry to fit on a single integrated circuit chip. The increased cache miss rate created by the reduced cache memory capacity is compensated for by the reduced cache miss resolution period resulting from integrating the main memory and processor on the single chip. The reduced cache miss resolution period enables the processor clock rate to be substantially increased, so that a processor having a simple functionality such as a reduced instruction set computer (RISC) processor can be utilized and still provide the required processing speed.

Abstract: A system for optimizing placement of a cell on a surface of a semiconductor chip is disclosed herein. The cells may belong to nets and may belong to neighborhoods. The system initially calculates affinities based on repositioning the cell. The system then combines affinities and repositions cells based on these combined affinities. The system then computes a cost function and repeats the combining, repositioning, and computing functions a predetermined number of times.

Abstract: The present invention presents a mobile station of a wireless communications system such that when the mobile station is in idle mode (i.e., listening to a paging channel periodically, but otherwise taking no action), the control processor commands the mobile station to enter into sleep mode to minimize power consumption. During sleep mode, the high-frequency reference clock and thus all high-frequency clocks derived from it are turned off. Only a low-frequency clock remains operating at all times to clock the sleep logic.

Abstract: According to the present invention comprises a plurality of diatonic note playing fret or key, each said diatonic note playing fret or key having a diatonic note playing surface and playing a corresponding diatonic note. Also included is a plurality of diatonic sheets, each said sheet comprising a note color associated with a particular diatonic note, wherein each said diatonic note playing surface has at least one diatonic sheet secured to it such that the note color comprising the sheet corresponds to the diatonic note played by the diatonic note playing fret or key.

Abstract: A method for maximizing effectiveness of parallel processing, using multiple processors, to connect pins of a net of an integrated circuit is disclosed. The method requires the pins to be partitioned into sets of pins and the sets of pins to be further partitioned into meta-sets of the sets of pins. The sets and the meta-sets are connected using a minimal spanning tree algorithm, and the connected sets are made to share a pin, thereby ensuring that the whole net is interconnected without creating a loop in the routing. In addition, because the partitions and the sets of partitions average approximately the same number of pins, the work load can easily be balanced between the processors.

Abstract: According to the present invention, a single chip semiconductor devices is provided. In one version of the invention, a single chip CMOS technology architecture is used to implement all or various combinations of baseband radio transmission, baseband interfaces and filtering, source coding, source interfaces and filtering, control and supervision, power and clock management, keyboard and display drivers, memory management and code compaction, digital signal processing ("DSP") and DSP memory and radio interface functions.

Abstract: A cell placement for an integrated circuit chip comprises a large number of cells allocated to respective locations on the surface of the chip. The placement is divided into switch boxes that surround the cell locations respectively. A bounding box is constructed around each net of a netlist for the placement. A congestion factor is computed for each switch box as being equal to the number of bounding boxes that overlap the respective switch box. A cost factor for the placement and associated netlist is computed as the maximum value, average value, sum of squares or other function of the congestion factors. The individual congestion factor computation can be modified to require that a pin of a net of one of the bounding boxes overlap or be within a predetermined distance of a switch box in order for the congestion factor to be computed as the sum of the overlapping bounding boxes in order to localize and increase the accuracy of the cost factor estimation.

Abstract: A computer implemented method for optimizing cell placement for integrated circuit design is provided herein. The method comprises the steps of segmenting an integrated circuit surface abstraction into a plurality of regions; assigning a plurality of cells to one of the regions; creating a list of said plurality of cells in order of decreasing cell height; reassigning said cells in order of the list such that the cells are assigned to said region until there is insufficient capacity to fit anymore of the cells into the region; and thereafter assigning the remaining cells outside of the region.