Abstract: For patterning during integrated circuit fabrication, a first pattern of first masking structures is formed, and a buffer layer is formed on exposed surfaces of the first masking structures. Also, a second pattern of second masking structures is formed in recesses between the buffer layer at sidewalls of the first masking structures. Furthermore, the first and masking structures are formed from spin-coating respective high carbon containing materials. Such first and second masking structures pattern a target layer with higher pitch than possible with traditional photolithography.

Abstract: A buffer amplifier includes an input stage and an output stage. The input stage has input high and low power voltages applied thereon for generating at least one transmission signal from an input signal. The output stage has output high and low power voltages applied thereon for generating an output signal from the at least one transmission signal. A first difference between the output high and low power voltages is less than a second difference between the input high and low power voltages for reducing the dynamic power consumption of the output stage.

Abstract: An image sensor includes a light receiving device, a field effect transistor, a stress layer pattern, and a surface passivation material. The light receiving device is formed in a first region of a substrate. The field effect transistor is formed in a second region of the substrate. The stress layer pattern is formed over the field effect transistor for creating stress therein to improve transistor performance. The surface passivation material is formed on the first region of the substrate for passivating dangling bonds at the surface of the light receiving device.

Abstract: For patterning during integrated circuit fabrication, an image layer is activated for forming a respective first type polymer block at each of two nearest activated areas. A layer of block copolymer is formed on the image layer, and a plurality of the first type polymer blocks and a plurality of second and third types of polymer blocks are formed on an area of the image layer between outer edges of the two nearest activated areas, from the block copolymer. At least one of the first, second, and third types of polymer blocks are removed to form a variety of mask structures.

Abstract: An apparatus for generating a VCOM voltage in a display device includes first and second buffer amplifiers and a charge pump. The first buffer amplifier is biased with high and low rail voltages for generating the VCOM voltage. The second buffer amplifier generates the high rail voltage at an output node not connected to an external capacitor. The charge pump generates the low rail voltage by charge pumping directly from an external power supply voltage. Alternatively, a charge pump and a comparator are used for generating the VCOM voltage at an output of the charge pump. The comparator generates a charge pump control signal from comparing the VCOM voltage with a reference voltage.

Abstract: An image sensor includes an active pixel and a black pixel. The active pixel has a first signal gain and a first dark signal level, and the black pixel has a second signal gain and a second dark signal level. At least one of the first and second signal gains is adjusted such that the first and second dark signal levels are substantially equal for minimizing image defects in the image sensor.

Abstract: A controller for processing a command in a data storage device includes at least one bitmap and a firmware command que. The at least one bitmap is formed in hardware to indicate that the command is received. The firmware command que is generated by firmware for storing the command when the at least one bitmap indicates receipt of the command. The firmware generates the firmware command que that is of variable size for processing a high number of commands. In addition, the bitmaps are generated in the hardware for quickly receiving the high number of commands.

Abstract: A three dimensional memory module and system are formed with at least one slave chip stacked over a master chip. Through semiconductor vias (TSVs) are formed through at least one of the master and slave chips. The master chip includes a memory core for increased capacity of the memory module/system. In addition, capacity organizations of the three dimensional memory module/system resulting in efficient wiring is disclosed for forming multiple memory banks, multiple bank groups, and/or multiple ranks of the three dimensional memory module/system.

Abstract: A depth sensor includes a light source, a detector, and a signal processor. The light source transmits a source signal to the target according to a transmit control signal having reference time points. The detector receives a reflected signal from the source signal being reflected from the target. The signal processor generates a plurality of sensed values by measuring respective portions of the reflected signal during respective time periods with different time delays from the reference time points. The signal processor determines a respective delay time for a maximum/minimum of the sensed values for determining the distance of the target.

Abstract: A multi-port memory device includes first and second ports, a first dedicated memory area assigned to the first port, a plurality of shared memory units having shared access by the first and second ports, a first set of I/O lines for the first dedicated memory area, and a second set of I/O lines for the shared memory units with the second set having more I/O lines than the first set. For example, the second set has N times more I/O lines than the first set, with N being a number of ports of the multi-port memory device or with N being a number of shared memory banks in a shared memory area.

Abstract: A data communication device or system includes a preamble unit and a data interface. The preamble unit generates or detects a first preamble having a first length for a first data line, and generates or detects a second preamble having a second length for a second data line. The first length is different from the second length, and data on the first and second data lines form parallel data. The data interface communicates a first data with the first preamble via the first data line and communicates a second data with the second preamble via the second data line. The respective length and/or respective pattern of each preamble are adjustable and/or programmable.

Abstract: A semiconductor device includes at least one first type of pad and at least one second type of pad having a different area from the first type of pad. A pad connection unit electrically couples the at least one second type of pad to an integrated circuit of the semiconductor device during a test mode, and disconnects the at least one second type of pad from the integrated circuit during a normal operating mode.

Abstract: For spatial resolution conversion of an image signal, a magnitude of a motion vector is compared to a threshold value. Single channel interpolation is performed if the magnitude of the motion vector is greater than a threshold value, and multi-channel interpolation is performed otherwise. In addition, single channel interpolation is performed for spatial resolution conversion of any frame that does not refer to another frame.

Abstract: A chip card receives and processes what-ever combination of contact data and contact-less data is available to allow multiple functionalities for the chip card. A micro-computer of the chip card is adapted to simultaneously receive and process contact data from a contact interface and contact-less data from a contact-less interface. In addition, the chip card includes a power voltage selector for selecting a contact bias to supply power to the micro-computer when-ever the contact bias voltage is available since the contact bias voltage is more stable than a contact-less bias voltage.

Abstract: A multi-port memory device includes a refresh register and a refresh controller for preventing refresh starvation in a shared memory unit of the memory device. The memory device further includes a plurality of ports sharing access to the shared memory unit. The refresh register stores information regarding at least one refresh command. The refresh controller determines whether to activate an internal refresh operation at a transition in port authority according to such information stored in the refresh register.

Abstract: A correlated double sampling unit in an image sensor includes a first capacitor, a second capacitor, and a capacitor switch. The first capacitor is coupled between a first node and an input node of a tripping unit. The second capacitor is coupled between the first node and a second node having a ramp signal switched thereon. The capacitor switch is coupled between the second node and the input node of the tripping unit for coupling the first and second capacitors in parallel as a final pixel signal is developed at the input node of the tripping unit for minimizing signal loss from a parasitic capacitance at the input node of the tripping unit.

Abstract: A liquid crystal panel includes a first type pixel and a second type pixel that are formed adjacent to each-other. The first type pixel has a first layout of respective first and second sub-pixels, and the second type pixel has a second layout of respective first and second sub-pixels. The first layout is different from the second layout such that the liquid crystal panel is driven according to dot inversion with alternating first and second sub-pixels determining the image displayed on the liquid crystal panel for preventing vertical faults.

Abstract: A multi-level phase change random access memory device includes a first electrode, a second electrode, and a phase change material disposed between the first electrode and the second electrode. The multi-level phase change random access memory device also includes a variable bias source coupled to the first electrode. The variable bias source provides a respective bias applied at the first electrode to form a portion of the phase change material to have one of an amorphous state and different crystal states for storing multi-bits data.

Abstract: An image sensor includes a logic region and an APS region having a first gate electrode, a photo-detector, a first protecting layer, first spacers, and a second protecting layer. The first gate electrode is formed over a semiconductor substrate. The photo-detector is formed to a side of the first gate electrode within the semiconductor substrate. The first protecting layer is formed over the first gate electrode and the photo-detector. The first spacers are formed over the first protecting layer to the sides of the first gate electrode. The second protecting layer is formed over the first protecting layer and the spacers. The first and second protecting layers are for preventing a contaminant from reaching the photo-detector.

Abstract: A bit-line sense amplifier includes a latching unit and a control unit. The latching unit has a plurality of field effect transistors coupled between first and second bit lines. The control unit controls application of a bias voltage to a set of the field effect transistors such that respective pre-charge voltages are generated at the first and second bit lines with drain currents flowing in the field effect transistors during a pre-charge time period, without a bit line bias voltage and with a minimized number of transistors.