Abstract: A source driver of a display panel includes a channel state signal generator, first switches, and second switches. The channel state signal generator generates first and second channel state signals that are each activated for a respective time period depending on adjustable state length data. The first switches are opened for uncoupling channel output signals from source lines of the display panel when the first channel state signal is activated. The second switches are closed for coupling together the source lines of the display panel for charge sharing when the second channel state signal is activated.

Abstract: A video decoder organizes and stores pixel lines of a reference picture into first and second memory devices. The video decoder then reads portions of a pixel block from the first and second memory devices and processes such a pixel block for generating a subsequent picture. By reading from the first and second memory device with time overlap, latency is minimized for faster video decoding.

Abstract: An averaging circuit includes an averaging unit and an offset compensation unit. The averaging unit generates an average signal from first and second input signals. The offset compensating unit is coupled to the averaging unit for conducting away bias currents from the averaging unit for preventing an offset in the average signal when any of the first and second input signals is too low or too high.

Abstract: A CMOS image sensor includes a plurality of active pixel rows and an optical black pixel row. The optical black pixel row is activated to generate a respective optical black signal upon activation of each of at least two of the active pixel rows. Such sharing of the optical black pixel row reduces the optical black area of the CMOS image sensor.

Abstract: A semiconductor device includes at least one first type of pad and at least one second type of pad having a different area from the first type of pad. A pad connection unit electrically couples the at least one second type of pad to an integrated circuit of the semiconductor device during a test mode, and disconnects the at least one second type of pad from the integrated circuit during a normal operating mode.

Abstract: For protecting data during transmission between a host device and a data storage device, the host device encrypts command-related information and sends the encrypted command-related information to the data storage device. The data storage device decrypts the encrypted command-related information, interprets the decrypted command-related information to generate interpreted commands, and executes the interpreted commands.

Abstract: Pairs of registers with reduced pins are disposed to overlap on front and back surfaces of a memory module. An input signal INS is transferred through the registers in series in a daisy chain fashion to avoid divergence of the input signal INS for preserved signal integrity. Each register buffers the input signal INS to memory banks disposed closely to sides of the register for reduced wiring area.

Abstract: A switched capacitor circuit includes an amplifier, a charging unit, an offset unit, and an integrating unit. The charging unit is coupled between an input node and a first node, and is for accumulating charge corresponding to an input signal during a sampling mode. The offset unit is coupled between the first node and an input of the amplifier, and is for maintaining the first node to be a virtual ground during an integrating mode. The integrating unit is coupled between the first node and an output of the amplifier, and is for receiving charge from the charging unit during the integrating mode.

Abstract: A driver circuit for a PRAM (phase-change random access memory) device includes a write driver that generates a set/reset current in response to a set/reset pulse. In addition, a temperature compensator controls a pulse width of the set/reset pulse in response to a peripheral temperature of the PRAM device. For example, the temperature compensator maintains the pulse width to be substantially constant irrespective of the peripheral temperature. In another example, the temperature compensator decreases the pulse width for higher peripheral temperature.

Abstract: A pulse width modulation (PWM) signal generator includes a quantizer for generating a quantized signal by quantizing an input signal, an asymmetric pulse width modulator, and an error correction unit. The asymmetric pulse width modulator generates an asymmetric PWM signal by comparing the quantized signal with a reference signal, with the asymmetric PWM signal being asymmetric with respect to a center of a period of the reference signal. The error correction unit is coupled between the quantizer and the asymmetric pulse width modulator to correct an error generated from the asymmetry of the asymmetric PWM signal. The quantizer is part of a delta sigma modulator having an operating frequency that is twice that of the reference signal.

Abstract: For fabricating a phase change memory cell, a layer of phase change material and a layer of a first electrode material are deposited. In addition, the first electrode material is patterned using an etchant including a low-reactivity halogen element such as bromine or iodine to form a first electrode. By using the low-reactivity halogen element, change to the composition of the phase change material and formation of undercut and deleterious halogen by-product are avoided.

Abstract: In a Gabor filter, a modified Gabor mask function is generated from an original Gabor mask function. A convolution of an image is performed with the modified Gabor mask function to generate a filtered image. The modification of the original Gabor mask function to the modified Gabor mask function reduces a number of calculations during such a convolution.

Abstract: An analog baseband circuit includes first and second DC (direct current) offset cancellers and an offset canceller controller. The first DC offset canceller includes a first filter and a first PGA (programmable gain amplifier) with a first gain step for eliminating a first dc component from an input baseband signal. The second DC offset canceller includes a second filter and a second PGA with a second gain step less than the first gain step for eliminating a second dc component from an output of the first DC offset canceller. The offset canceller controller controls the first and second filters to operate in a fast mode when a gain of the first PGA is changed.

Abstract: An image sensor includes a pixel with a drive transistor and a select transistor. The drive transistor is driven according to a voltage at a floating diffusion node. The select transistor is coupled in series with the drive transistor for being turned on when the pixel is selected. The image sensor also includes a current mirror unit having first and second branches conducting mirrored currents. The first branch is coupled to the drive transistor, and the second branch is coupled to the select transistor at an output node of the pixel. With such biasing by the current mirror, gain drop in the drive transistor is minimized.

Abstract: A semiconductor fuse box includes a fuse structure and a protective structure disposed between the fuse structure and an integrated circuit structure. The protective structure has at least one irregular side surface. The protective structure (which may also include a pad formed there-under) extends beyond a bottom of the fuse structure. Such an irregular side surface and such an extension of the protective structure minimize propagation of damaging energy to the adjacent integrated circuit structure when a laser beam is directed to the fuse structure.

Abstract: An analog-to-digital converter in an image sensor is implemented with a plurality of comparator units. Each comparator unit has a respective capacitor array and respective switches integrated therein. Such capacitors and switches across the comparator units are operated for generating ramp voltages for such comparator units for performing analog-to-digital conversion with correlated double sampling. Thus, circuit area and power consumption of the CMOS image sensor may be minimized.

Abstract: An image-sensing device includes a driver and an array of pixels. The driver controls the array of pixels to output a combined image signal that is a combination of at least two image signals for at least two aligned pixels in at least two rows, for reducing vertical resolution in the sub-sampling mode. In addition, a mixing circuit further averages the resulting combined signals for M consecutive odd or even columns for reducing horizontal resolution in the sub-sampling mode.

Abstract: An integrated circuit includes first and second power domains, a power supply control unit, and a switch block. The power supply control unit supplies a first voltage to the first power domain and a second voltage to the second power domain. The switch block provides at least one current path between the first and second power domains during a predetermined operating mode such as by connecting a first power line of the first power domain to a second power line of the second power domain.

Abstract: A display device includes a first set of data buses coupled between a timing controller and a first line driver. In addition, the display device also includes a second set of at least one data bus coupled between the first line driver and a second line driver. The second set has a less number of at least one data bus than the first set. Thus, data signals are transmitted to the line drivers of the display panel from the timing controller with minimized wiring for reduced power consumption and electromagnetic interference.

Abstract: For fabricating multiple field effect transistors (FETs), a first conductive layer is deposited over first and second active regions of a semiconductor substrate. The first conductive layer is patterned over the second active region to form mold structures. Mask structures are formed between the mold structures. The second active region is patterned using the mask structures or using spacers formed at sidewalls of the mold structures to form multiple fins of a field effect transistor of a fin type. The first conductive layer is patterned over the first active region to form a gate of another field effect transistor of a different type.