Patents Represented by Attorney, Agent or Law Firm Mueting & Raasch
  • Patent number: 8199558
    Abstract: Variable resistive punchthrough access methods are described. The methods include switching a variable resistive data cell from a high resistance state to a low resistance state by passing a write current through the magnetic tunnel junction data cell in a first direction. The write current is provided by a transistor being electrically coupled to the variable resistive data cell and a source line. The write current passes through the transistor in punchthrough mode.
    Type: Grant
    Filed: March 8, 2011
    Date of Patent: June 12, 2012
    Assignee: Seagate Technology LLC
    Inventors: Maroun Georges Khoury, Hongyue Liu, Brian Lee, Andrew John Gjevre Carter
  • Patent number: 8199564
    Abstract: Methods of writing to a multi-bit MRAM memory unit are described. The method includes to self-detected writing to a multi-bit (i.e., multilevel) thermally assisted MRAM. The self-detected writing increases a reading margin between data state levels and decreases reading margin variability due to cell resistance variation.
    Type: Grant
    Filed: June 15, 2011
    Date of Patent: June 12, 2012
    Assignee: Seagate Technology LLC
    Inventors: Yuankai Zheng, Dimitar V. Dimitrov, Haiwen Xi
  • Patent number: 8199563
    Abstract: A transmission gate-based spin-transfer torque memory unit is described. The memory unit includes a magnetic tunnel junction data cell electrically coupled to a bit line and a source line. A NMOS transistor is in parallel electrical connection with a PMOS transistor and they are electrically connected with the source line and the magnetic tunnel junction data cell. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a polarized write current through the magnetic tunnel junction data cell. The PMOS transistor and the NMOS transistor are separately addressable so that a first write current in a first direction flows through the PMOS transistor and a second write current in a second direction flows through the NMOS transistor.
    Type: Grant
    Filed: May 31, 2011
    Date of Patent: June 12, 2012
    Assignee: Seagate Technology LLC
    Inventors: Yiran Chen, Hai Li, Hongyue Liu, Yong Lu, Yang Li
  • Patent number: 8198252
    Abstract: The present invention provides polynucleotides, compositions including polynucleotides, and the uses thereof for treating cancer in a subject. The polynucleotides silence the expression of coding regions that encode polypeptides such as p85?, p110?, and Akt2. The cancers treatable using the methods described herein include colorectal cancer, breast cancer, lung cancer, and metastases thereof.
    Type: Grant
    Filed: May 18, 2007
    Date of Patent: June 12, 2012
    Assignee: Board of Regents, The University of Texas System
    Inventors: B. Mark Evans, Piotr G. Rychahou
  • Patent number: 8198181
    Abstract: A switching element that includes a first semiconductor layer, the first semiconductor layer having a first portion and a second portion; a second semiconductor layer, the second semiconductor layer having a first portion and a second portion; an insulating layer disposed between the first semiconductor layer and the second semiconductor layer; a first metal contact in contact with the first portion of the first semiconductor layer forming a first junction and in contact with the first portion of the second semiconductor layer forming a second junction; a second metal contact in contact with the second portion of the first semiconductor layer forming a third junction and in contact with the second portion of the second semiconductor layer forming a fourth junction, wherein the first junction and the fourth junction are Schottky contacts, and the second junction and the third junction are ohmic contacts.
    Type: Grant
    Filed: February 20, 2012
    Date of Patent: June 12, 2012
    Assignee: Seagate Technology LLC
    Inventors: Young Pil Kim, Nurul Amin, Dadi Setiadi, Venugopalan Vaithyanathan, Wei Tian, Insik Jin
  • Patent number: 8198660
    Abstract: A multi-bit spin torque magnetic element that has a ferromagnetic pinned layer having a pinned magnetization orientation, a non-magnetic layer, and a ferromagnetic free layer having a magnetization orientation switchable among at least four directions, the at least four directions being defined by a physical shape of the free layer. The magnetic element has at least four distinct resistance states. Magnetic elements with at least eight magnetization directions are also provided.
    Type: Grant
    Filed: August 27, 2010
    Date of Patent: June 12, 2012
    Assignee: Seagate Technology LLC
    Inventors: Dimitar V. Dimitrov, Zheng Gao, Xiaobin Wang
  • Patent number: 8199565
    Abstract: A magnetic data storage cell, applicable to spin-torque random access memory (ST-RAM), is disclosed. A magnetic cell includes first and second fixed magnetic layers and a free magnetic layer positioned between the fixed magnetic layers. The magnetic cell also includes terminals configured for providing a spin-polarized current through the magnetic layers. The first fixed magnetic layer has a magnetization direction that is substantially parallel to the easy axis of the free magnetic layer, and the second fixed magnetic layer has a magnetization direction that is substantially orthogonal to the easy axis of the free magnetic layer. The dual fixed magnetic layers provide enhanced spin torque in writing to the free magnetic layer, thereby reducing the required current and reducing the feature size of magnetic data storage cells, and increasing the data storage density of magnetic spin torque data storage.
    Type: Grant
    Filed: August 16, 2011
    Date of Patent: June 12, 2012
    Assignee: Seagate Technology LLC
    Inventors: Thomas W. Clinton, Michael A. Seigler
  • Patent number: 8199569
    Abstract: A memory array includes a cross-point array of bit and source lines. A memory is disposed at cross-points of the cross-point array. The memory unit includes a magnetic tunnel junction data cell electrically coupled to a bit line and a source line. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a polarized write current through the magnetic tunnel junction data cell. A transistor is electrically between the magnetic tunnel junction data cell and the bit line or source line and a diode is in thermal or electrical contact with the magnetic tunnel junction data cell to assist in resistance state switching.
    Type: Grant
    Filed: April 15, 2011
    Date of Patent: June 12, 2012
    Assignee: Seagate Technology LLC
    Inventors: Xuguang Wang, Yiran Chen, Dimitar V. Dimitrov, Hongyue Liu, Xiaobin Wang
  • Patent number: 8191238
    Abstract: A magnetic writer comprises a write pole, a substrate and a non-magnetic, oxygen-free buffer material. The write pole has a leading edge, a trailing edge, a first side and second side. The substrate is at the leading edge of the write pole. The non-magnetic, oxygen-free buffer material is located between the write pole and the substrate.
    Type: Grant
    Filed: June 22, 2009
    Date of Patent: June 5, 2012
    Assignee: Seagate Technology LLC
    Inventors: Alexandre Vasilievish Demtchouk, Thomas Roy Boonstra, Michael Christopher Kautzky
  • Patent number: 8191407
    Abstract: Probe structures that utilize a folded beam structure to support the probe tip. The folded beam or supported-beam structure provides a linear spring force over a large displacement range while resisting probe tip tilting and lateral motion of the probe tip. In one embodiment, the probe structure has a supported-beam structure comprising an inner beam structure surrounded by an outer support, the inner beam structure pivotally connected to the outer support. The inner beam structure has a central region and the outer support having outer corner regions. The outer corner regions provide an attachment region to a supporting mechanism for the probe structure. A probe tip is located at the central region of the inner beam structure. The probe structure may have at least three arms, for example, four arms.
    Type: Grant
    Filed: May 13, 2008
    Date of Patent: June 5, 2012
    Assignee: Seagate Technology LLC
    Inventor: Wayne Allen Bonin
  • Patent number: 8192653
    Abstract: A fire suppression composition includes starch, a pseudo-plastic, high yield, suspending agent, paraffin or olefin, and a neutralizer.
    Type: Grant
    Filed: September 27, 2010
    Date of Patent: June 5, 2012
    Assignee: EarthCleanCorporation
    Inventors: James Alroy E. Hagquist, Robert M. Hume, III, Terrance L. Lund, Roderick I. Lund
  • Patent number: 8194444
    Abstract: Self-reference reading a magnetic tunnel junction data cell methods are disclosed. An illustrative method includes applying a read voltage across a magnetic tunnel junction data cell and forming a read current. The magnetic tunnel junction data cell has a first resistance state. The read voltage is sufficient to switch the magnetic tunnel junction data cell resistance. The method includes detecting the read current and determining if the read current remains constant during the applying step. If the read current remains constant during the applying step, then the first resistance state of the magnetic tunnel junction data cell is the resistance state that the read voltage was sufficient to switch the magnetic tunnel junction data cell to.
    Type: Grant
    Filed: December 15, 2010
    Date of Patent: June 5, 2012
    Assignee: Seagate Technology LLC
    Inventors: Yuankai Zheng, Yiran Chen, Xiaobin Wang, Zheng Gao, Dimitar V. Dimitrov, Wenzhong Zhu, Yong Lu
  • Patent number: 8187732
    Abstract: A lubricant layer for a magnetic recording medium may include a perfluoropolyether having monomer units and end groups selected to provide high thermal stability and good reliability.
    Type: Grant
    Filed: November 13, 2009
    Date of Patent: May 29, 2012
    Assignee: Seagate Technology LLC
    Inventors: Lei Li, Xiaoping Yan, Paul M. Jones, Jiping Yang, Yiao-Tee Hsia
  • Patent number: 8189294
    Abstract: An apparatus that includes a write element including a write element tip having a leading edge, a trailing edge, and first and second side edges connecting the leading edge to the trailing edge, wherein the trailing edge is non-planar; a trailing shield proximate the trailing edge of the write element; a first side shield proximate the first side edge; and a second edge proximate the second side edge.
    Type: Grant
    Filed: June 21, 2010
    Date of Patent: May 29, 2012
    Assignee: Seagate Technology LLC
    Inventors: Harry Sam Edelman, David Christopher Seets, Mourad Benakli, Kirill Aleksandrovich Rivkin
  • Patent number: 8183653
    Abstract: A magnetic tunnel junction includes an amorphous ferromagnetic reference layer having a first reference layer side and an opposing second reference layer side. The first reference layer side has a greater concentration of boron than the second reference layer side. A magnesium oxide tunnel barrier layer is disposed on the second side of the amorphous ferromagnetic reference layer. The magnesium oxide tunnel barrier layer has a crystal structure. An amorphous ferromagnetic free layer is disposed on the magnesium oxide tunnel barrier layer.
    Type: Grant
    Filed: July 13, 2009
    Date of Patent: May 22, 2012
    Assignee: Seagate Technology LLC
    Inventors: Xilin Peng, Konstantin Nikolaev, Taras Pokhil, Victor Sapazhnikov, Yonghua Chen
  • Patent number: 8183126
    Abstract: Various embodiments of the present invention are generally directed to an apparatus with embedded (bottom side) control lines for vertically stacked semiconductor elements, and a method for forming the same. In accordance with various embodiments, a first semiconductor wafer is provided with a first facing surface on which a first conductive layer is formed. The first semiconductor wafer is attached to a second semiconductor wafer to form a multi-wafer structure, the second semiconductor wafer having a second facing surface on which a second conductive wafer is formed. The first conductive layer is contactingly bonded to the second conductive layer to form an embedded combined conductive layer within said structure. Portions of the combined conductive layer are removed to form a plurality of spaced apart control lines that extend in a selected length or width dimension through said structure.
    Type: Grant
    Filed: July 13, 2009
    Date of Patent: May 22, 2012
    Assignee: Seagate Technology LLC
    Inventors: Hyung-Kyu Lee, YoungPil Kim, Peter Nicholas Manos, Maroun Khoury, Dadi Setiadi, Chulmin Jung, Hsing-Kuen Liou, Paramasiyan Kamatchi Subramanian, Yongchul Ahn, Jinyoung Kim, Antoine Khoueir
  • Patent number: 8182460
    Abstract: A fluid infusion device and a method of using the same. The device includes an outer, flexible guide catheter having a distal end for introduction beneath the skull of a patient and a proximal end remaining external of the patient. A flexible infusion fiber is located within the guide catheter and has a distal end extending outwardly from the guide catheter to be located in a target area within the patient's brain. The infusion fiber can be fixed or axially movable within the guide catheter. In the latter embodiment, the proximal end of the infusion fiber extending outwardly from the guide catheter can be manipulated to locate the distal end of the infusion fiber in the target area. An infusion pump is connected to the proximal end of the infusion fiber to infuse a minute quantity of fluid at an extremely low flow rate into the brain of the patient.
    Type: Grant
    Filed: February 9, 2010
    Date of Patent: May 22, 2012
    Assignee: Medtronic, Inc.
    Inventors: Michael G. Kaplitt, Matthew J. During
  • Patent number: 8178864
    Abstract: A diode having a reference voltage electrode, a variable voltage electrode, and a diode material between the electrodes. The diode material is formed of at least one high-K dielectric material and has an asymmetric energy barrier between the reference voltage electrode and the variable voltage electrode, with the energy barrier having a relatively maximum energy barrier level proximate the reference voltage electrode and a minimum energy barrier level proximate the variable voltage electrode.
    Type: Grant
    Filed: November 18, 2008
    Date of Patent: May 15, 2012
    Assignee: Seagate Technology LLC
    Inventors: Insik Jin, Wei Tian, Venugopalan Vaithyanathan, Cedric Bedoya, Markus Siegert
  • Patent number: 8179716
    Abstract: Spin torque magnetic logic device having at least one input element and an output element. Current is applied through the input element(s), and the resulting resistance or voltage across the output element is measured. The input element(s) include a free layer and the output element includes a free layer that is electrically connected to the free layer of the input element. The free layers of the input element and the output element may be electrically connected via magnetostatic coupling, or may be physically coupled. In some embodiments, the output element may have more than one free layer.
    Type: Grant
    Filed: November 24, 2010
    Date of Patent: May 15, 2012
    Assignee: Seagate Technology LLC
    Inventors: Haiwen Xi, Yang Li, Song S. Xue
  • Patent number: 8179712
    Abstract: A resistive memory cell that includes a metal-polymer bi-layer proximate a CMOS gate. The memory cell has a substrate having a source contact connected to a source line and a drain contact connected to a drain line, a CMOS gate proximate the substrate electrically connecting the source contact and the drain contact, the bi-layer adjacent the CMOS gate, the bi-layer comprising a thin metal layer and a polymer layer, and a word line connected to the bi-layer.
    Type: Grant
    Filed: June 25, 2009
    Date of Patent: May 15, 2012
    Assignee: Seagate Technology LLC
    Inventor: Jun Zheng