Abstract: In an embodiment, a communication device is provided comprising transmit circuitry and crosstalk reduction circuitry. In an embodiment, the crosstalk reduction circuitry is configured to receive crosstalk information indicative of crosstalk between a plurality of communication connections for only a part of communication channels of said communication connections.

Abstract: A semiconductor component includes at least one field effect transistor disposed along a trench in a semiconductor region and has at least one locally delimited dopant region in the semiconductor region. The at least one locally delimited dopant region extends from or over a pn junction between the source region and the body region of the transistor or between the drain region and the body region of the transistor into the body region as far as the gate electrode, such that a gap between the pn junction and the gate electrode in the body region is bridged by the locally delimited dopant region.

Abstract: A semiconductor component includes a semiconductor body having a first surface and a second surface, and having an inner region and an edge region. The semiconductor component further includes a pn-junction between a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type, the pn-junction extending in a lateral direction of the semiconductor body in the inner region. A first trench extends from the first side in the edge region into the semiconductor body. The trench has sidewalls that are arranged opposite to another and that are beveled relative to a horizontal direction of the semiconductor body.

Abstract: A semiconductor device as described herein includes a body region of a first conductivity type adjoining a channel region of a second conductivity at a first side of the channel region. A gate control region of the first conductivity type adjoins the channel region at a second side of the channel region opposed to the first side, the channel region being configured to be controlled in its conductivity by voltage application between the gate control region and the body region. A source zone of the second conductivity type is arranged within the body region and a channel stop zone of the second conductivity type is arranged at the first side, the channel stop zone being arranged at least partly within at least one of the body region and the channel region. The channel stop zone includes a maximum concentration of dopants lower than a maximum concentration of dopants of the source zone.

Abstract: According to an embodiment of a method of manufacturing a power transistor module, the method includes mechanically fastening a first terminal, a second terminal and at least two different DC bias terminals to an electrically conductive flange; connecting the flange to a source of a power transistor device; electrically connecting the first terminal to a gate of the power transistor device; electrically connecting the second terminal to a drain of the power transistor device; mechanically fastening a bus bar to the flange which extends between and connects the DC bias terminals; and electrically connecting the bus bar to the drain via one or more RF grounded connections.

Abstract: An integrated circuit is described. The integrated circuit may comprise a multitude of floating-gate electrodes, wherein at least one of the floating-gate electrodes has a lower width and an upper width, the lower width being larger than the upper width, and wherein the at least one of the floating-gate electrodes comprises a transition metal. A corresponding manufacturing method for an integrated circuit is also described.

Abstract: A semiconductor component includes a body with a drift zone, a source zone, a body zone, and a drain zone. A gate forms a MOS structure with the drift zone, with the source zone and with the body zone. An edge termination between the lateral edge and the MOS structure includes a plurality of field rings which enclose the MOS structure. The lateral edge is at the same potential as the drift zone, and the edge termination reduces voltage between the lateral edge and the source zone. A horizontally extending edge plate is disposed at the front side between the lateral edge and the edge termination. The edge plate is at the same potential as the drift zone and forms a plate capacitor structure including a field plate lying above the edge plate.

Abstract: A high-definition multimedia interface (HDMI) plug on an HDMI cable assembly includes an indicator light that is illuminated only when both ends of the cable are plugged into a video source and a video sink. Embodiments include an HDMI plug that comprises a connector body having a mating end configured for insertion into a mating HDMI receptacle and containing electrical pins configured according to HDMI specifications, the pins including a +5V Power pin, a Ground pin, and a Hot Plug Detect pin. The HDMI plug further comprises an indicator circuit that includes a light-emitting diode and a transistor switch in series with the light emitting-diode, wherein the light-emitting diode and transistor switch are coupled to the +5V Power pin, Ground pin, and Hot Plug Detect pin so that the light-emitting diode is activated only when both the +5V Power pin and Hot Plug Detect pin are energized.

Abstract: A depletion transistor includes a source region and a drain region of a first conductivity type, a channel region of the first conductivity type arranged between the source region and the drain region and a first gate electrode arranged adjacent the channel region and dielectrically insulated from the channel region by a gate dielectric. The depletion transistor further includes a first discharge region of a second conductivity type arranged adjacent the gate dielectric and electrically coupled to a terminal for a reference potential. The depletion transistor can be included in a charging circuit.

Abstract: A memory arrangement comprises a first memory module and a second memory module. An item of information to be written to the memory arrangement is written with a first address both to the first memory module and to the second memory module. When reading, the item of information is read either from the first memory module by means of the first address or from the second memory module by means of a second address differing from the first address. Subsequently a check is made as to whether the item of information is defective. If this is the case, the item of information is read from the respective other memory module.

Abstract: A dual loop (PLL/DLL) data synchronization system and method for plesiochronous systems is provided. A dual loop data serializer includes a phase lock loop (PLL) and a delayed lock loop (DLL) configured with a phase shifter in the feedback path of the PLL. The dual loop serializer locks to the input of the DLL instead of the local reference. Thus, the DLL adjusts the frequency from the PLL so that it matches the desired data rate. Each loop may be optimized for jitter tolerance with the net effect generating a synthesized clean clock (due to narrow bandwidth filtering) and VCO noise suppression (due to wide bandwidth filtering). A dual loop retimer includes a dual loop serializer (PLL/DLL) and a clock recovery DLL. The retimer resets the jitter budget to meet transmission requirements for an infinite number of repeater stages.

Abstract: The power semiconductor module (1) comprises several semiconductor components (6, 7, 8), located on a substrate (2). The aim of the invention is to prevent a reduction in the pressure of the substrate against a cooling surface and the resulting loss of cooling arising from deformations. Said aim is achieved, whereby the substrate (2) comprises several substrate regions (3, 4, 5), with one or several connection regions (31, 32), located between substrate regions (3, 4, 5), by means of which the substrate regions (3, 4, 5) are connected such as to move relative to each other.

Abstract: A power semiconductor module includes a normally on, controllable first power semiconductor switch including at least one first power semiconductor chip, and a normally off, controllable second power semiconductor switch including at least one second power semiconductor chip. The load paths of the first power semiconductor switch and of the second power semiconductor switch are connected in series. The control terminals of all first power semiconductor chips are permanently electrically conductively connected to a conductor track to which no load terminal of any of the first power semiconductor chips is permanently electrically conductively connected, and to which no load terminal and no control terminal of any of the second power semiconductor chips are permanently electrically conductively connected.

Abstract: A method for producing a housing part for a power semiconductor module includes providing a connecting lug having a lower end with a foot region, providing a housing having a side wall with a lead-in bevel, and inserting the connecting lug into the lead-in bevel so that the foot region projects inward into an interior of the housing. The method further includes encapsulating at least a portion of the foot region of the connecting lug inserted into the lead-in bevel with a first plastic to produce a positively locking first connection between the connecting lug and the side wall.

Abstract: An embodiment of the invention relates to a circuit assembly having the following components: a power transistor with a control terminal, a first load terminal and a second load terminal, the second load terminal having a floating potential; a driver circuit configured to generate control signals for the control terminal of the power transistor, the relevant reference potential for the driver circuit being the floating potential of the second load terminal; a planar metallization layer sited on or in a substrate and comprising a constant reference potential, a shielding plane isolated from the metallization layer, sited planar on or in the substrate such that it is capacitively coupled to the metallization layer; a power supply circuit for providing a supply voltage referenced to the floating potential of the second load terminal for the driver circuit, the power supply circuit comprising, circuited between the second load terminal and the shielding plane, a first series circuit including a first capacitor an

Abstract: An arrangement for mounting a multiplicity of components (9, 10), particularly with irregular surface topography, on a support (7) using an assembly tool which has a tool substructure (5) and a tool superstructure (6), where the tool substructure (5) is designed to receive the support and the components which are to be mounted thereon, and the tool superstructure (6) has, in addition to an arrangement (11, 12) for transmitting assembly forces, an arrangement for compensating for tilts between the components and the support and/or an arrangement for compensating for irregular surface topologies.

Abstract: Methods and apparatus for power supply load dump compensation according to various aspects of the present invention may operate in conjunction with a power stage system, such as a power stage system comprising a bootstrapped driver circuit and a power stage responsive to the driver circuit. The power stage system may further include a load dump compensation circuit connected to the driver circuit, wherein the load dump compensation circuit is configured to remove a bias current generated by the bootstrapped driver circuit. Various aspects of the present invention may be implemented in conjunction with any appropriate power supply, such as a switching regulator, for example a buck converter.

Abstract: According to an embodiment of a communication device, the communication device includes communication circuitry configured to communicate via a plurality of transmission channels. The communication circuitry includes crosstalk reduction circuitry to reduce crosstalk for a part of the plurality of transmission channels by joint processing of data of the part of the transmission channels. This part is selected from the plurality of transmission channels depending on a grouping of the transmission channels into at least two groups. Each of the at least two groups is assigned a target bit rate. The target bit rate differs for different groups.

Abstract: Disclosed is a power regulator for providing precisely regulated power to a microelectronic device such as a microprocessor. Improved power regulation is accomplished by optimizing the power efficiency of the power regulator. In particular, in a multiphase system, the number of active phases is increased or decreased to achieve optimum power efficiency. The multiphase voltage regulator adapts the operating mode to maximize efficiency as the load current demand of the load device changes by adjusting the number of active phases to maximize efficiency. The total value of current provided by the regulator and the total number of active phases is determined, the total number of active phases is compared with the number of active phases required to provide the total value of current at maximum efficiency; and the number of active phases is adjusted to provide the total value of current at maximum efficiency.

Abstract: An amplifier circuit includes a signal summing node, a first amplifier configured to operate in a first mode, an impedance inverter, a second amplifier configured to operate in a second mode and a wideband impedance transformer. The impedance inverter couples an output of the first amplifier to the signal summing node. The impedance inverter is configured to provide impedance transformation and load modulation to the first amplifier. The second amplifier has an output coupled to the signal summing node. The wideband impedance transformer has a first end coupled to the signal summing node and a second end forming a terminal node. The wideband impedance transformer is configured to present a real impedance to the first amplifier over at least 25% of a radio frequency bandwidth of the amplifier circuit.