Abstract: Methods, systems and/or computer program products are provided for managing Quality of Service (QoS) and/or bandwidth allocation in a Regional/Access Network (RAN) having a broadband access server (BRAS) that facilitates differentiated end-to-end data transport between a Network Service Provider (NSP) and/or an Application Service Provider (ASP), and a Customer Premises Network (CPN) that includes a Routing Gateway (RG). In particular embodiments of the present invention, a modify QoS and/or bandwidth allocation message including updated QoS and/or bandwidth information from the NSP and/or ASP is received at the RAN. The BRAS is updated with the QoS and/or bandwidth information and the RG is also updated with the QoS and/or bandwidth information.

Abstract: The present invention relates to enzymatic activity involved in isoprenoid biosynthesis as well as to inhibitors, notably herbicides, for enzymes in the biosynthesis of isoprenoids. More specifically, the present invention relates to screening methods for detecting such inhibitors, and to enzymatically active proteins for performing said methods as well as purified isolated DNA coding for such proteins. Moreover, the present invention relates to novel inhibitors detectable by said screening methods as well as compositions and processes for inhibiting the synthesis of isoprenoids and for controlling the growth of organisms based on said inhibitors. The invention relates also to the development of inhibitor-resistant plant enzymes and plants, plant tissues, plant seeds and plant cells.

Abstract: Methods of forming CMOS integrated circuit devices include forming at least first, second and third transistors in a semiconductor substrate and then covering the transistors with one or more electrically insulating layers that impart a net stress (tensile or compressive) to channel regions of the transistors. The covering step may include covering the first and second transistors with a first electrically insulating layer having a sufficiently high internal stress characteristic to impart a net tensile (or compressive) stress in a channel region of the first transistor and covering the second and third transistors with a second electrically insulating layer having a sufficiently high internal stress characteristic to impart a net compressive (or tensile) stress in a channel region of the third transistor. A step may then performed to selectively remove a first portion of the second electrically insulating layer extending opposite a gate electrode of the second transistor.

Abstract: A memory device and method of reading the memory device is disclosed. The memory device includes a first string of MRAM cells and a second string of MRAM cells. The first string of MRAM cells include a plurality of MRAM cells connected in series and the second string of MRAM cells include another plurality of MRAM cells connected in series. A common connection is controllably connectable to one end of the first string of MRAM cells, and to one end of the second string of MRAM cells.

Abstract: MOS transistors have an active region defined in a portion of a semiconductor substrate, a gate electrode on the active region, and drain and source regions in the substrate. First and second lateral protrusions extend from the lower portions of respective sidewalls of the gate electrode. The drain region has a first lightly-doped drain region under the first lateral protrusion, a second lightly-doped drain region adjacent the first lightly-doped drain region, and a heavily-doped drain region adjacent to the second lightly-doped drain region. The source region similarly has a first lightly-doped source region under the second lateral protrusion, a second lightly-doped source region adjacent the first lightly-doped source region, and a heavily-doped source region adjacent to the second lightly-doped source region. The second lightly-doped regions are deeper than the first lightly-doped regions, and the gate electrode may have an inverted T-shape.

Abstract: A mobile terminal may include a wireless modem, a wireless network interface, and an application (such as a browser application). A method of operating the mobile terminal may include providing a first data path between a data network and the application of the mobile terminal through the wireless modem. In addition, a second data path may be provided between the data network and second mobile terminal through the wireless modem and the wireless network interface of the first mobile terminal. Related devices are also discussed.

Abstract: Methods of processing a semiconductor structure including a metal layer in the presence of organic material include flowing an aqueous mixture including an oxidizing agent over the semiconductor structure during processing of the semiconductor structure. Processing the semiconductor structure may include sawing the semiconductor structure and/or scrubbing the semiconductor structure with pressurized water. The oxidizing agent may include a peroxide, such as hydrogen peroxide, or another oxidizing agent.

Abstract: A light-emitting device comprises a substrate that has a contact plug extending therethrough between first and second opposing surfaces. An active region is on the first surface, a first electrical contact is on the active region, and a second electrical contact is adjacent to the second surface of the substrate. The contact plug couples the second electrical contact to the active region. Such a configuration may allow electrical contacts to be on opposing sides of a chip, which may increase the number of devices that may be formed on a wafer.

Abstract: An input device includes a plurality of MRAM cells and a layer of particles. An MRAM cell in the input device includes a sense layer having a magnetic orientation. At least one particle of the layer of particles is located near the MRAM cell such that the particle affects the magnetic orientation of the sense layer of the MRAM cell.

Abstract: A Universal Serial Bus (USB) modem device includes a body member and a flip member. The flip member includes an antenna element and is rotatably coupled to the body member for movement about a hinge axis between a closed position and an open position. A USB connector is movably mounted in the body member for movement between an extended position and a retracted position relative to the body member. A linkage mechanism in the body member couples the flip member and the USB connector so that movement of the flip member between the open position and the closed position moves the USB connector between the extended position and the retracted position.

Abstract: An integrated circuit device may include a substrate, a conductive pad on a surface of the substrate, and a conductive line on the surface of the substrate. Moreover, the conductive line may be connected to the conductive pad, and the conductive line may be narrow relative to the conductive pad. In addition, an insulating layer may be provided on the substrate, on the conductive line, and on edge portions of the conductive pad. The insulating layer may have a hole therein exposing a central portion of the conductive pad, and a first segment of a perimeter of the hole may substantially define an arc of a circle around the central portion of the conductive pad. A second segment of the perimeter of the hole may substantially deviate from the circle around the central portion of the conductive pad, and the second segment of the perimeter of the hole may be adjacent a connection between the conductive line and the conductive pad.

Abstract: The systems, methods and associated devices performing diagnostic hearing tests which use a computer network to allow interaction between a test administration site and one or a plurality of remote patient sites. The test can be administered by an audiologist or clinician at a site remote from the patient, in a manner, which can allow interaction between the user and the clinician during at least a portion of the administration of the test. The diagnostic hearing tests can be performed such that they meet standardized guidelines such as ANSI requirements or certification standards and can include distortion product emission level measurements or middle ear compliance measurements.

Abstract: A semiconductor device has two transistors of different structure from each other. One of transistors is P-type and the other is N-type. One of the transistors includes a gate structure in which a polysilicon layer contacts a gate insulation film while the other transistor includes a gate structure in which a metal layer contacts a gate insulation film.

Abstract: Methods and apparatus are configured to provide data to render (medical) images using direct volume rendering by electronically analyzing a medical volume data set associated with a patient that is automatically electronically divided into a plurality of local histograms having intensity value ranges associated therewith and programmatically generating data used for at least one of tissue detection or tissue classification of tissue having overlapping intensity values.

Abstract: Trench capacitors that have insulating layer collars in undercut regions and methods of fabricating such trench capacitors are provided. Some methods of fabricating a trench capacitor include forming a first layer on a substrate. A second layer is formed on the first layer opposite to the substrate. A mask is formed that has an opening on top of the first and second layers. A first trench is formed by removing a portion of the first and second layers through the opening in the mask. A portion of the first layer under the second layer is removed to form an undercut region under the second layer. An insulating layer collar is formed in the undercut region under the second layer. A second trench is formed that extends from the first trench by removing a portion of the substrate through the opening in the mask. A buried plate is formed in the substrate along the second trench. A dielectric layer is formed on an inner wall and bottom of the second trench.

Abstract: Field effect transistors include a substrate and a pillar that extends away from the substrate. The pillar includes a base adjacent the substrate, a top remote from the substrate, and a sidewall that extends between the base and the top. An insulated gate is provided on the sidewall. A first source/drain region is provided in the substrate beneath the pillar and adjacent the insulated gate. A second source/drain region that is heavily doped compared to the first source/drain region, is provided in the substrate beneath the pillar and remote from the insulated gate. The pillar may be an I-shaped pillar that is narrower between the base and the top compared to adjacent the base and the top, such that the sidewall includes a recessed portion between the base and the top.

Abstract: The use of human erythropoietin (EPO) to prevent or treat endothelial injury due to chemotherapy, radiation therapy, mechanical trauma, or to a disease state which damages the endothelium (such as inflammation, heart disease or cancer) is described. The use of EPO in conjunction with the administration of chemotherapeutic agents is described.

Abstract: Methods of forming a metal salicide layer can include forming a metal layer on a substrate and forming a metal silicide layer on the metal layer using a first thermal process at a first temperature. Then a second process is performed, in-situ with the first thermal process, on the metal layer at a second temperature that is less than the first temperature.

Abstract: Semiconductor memory devices include a semiconductor substrate and a plurality of semiconductor material pillars in a spaced relationship on the semiconductor substrate. Respective surrounding gate electrodes surround ones of the pillars. A first source/drain region is in the semiconductor substrate between adjacent ones of the pillars and a second source/drain region is in an upper portion of at least one of the adjacent pillars. A buried bit line is in the first source/drain region and electrically coupled to the first source/drain region and a storage node electrode is on the upper portion of the at least one of the adjacent pillars and electrically contacting with the second source/drain region.

Abstract: A method of programming a nonvolatile memory device including a plurality of memory cells includes providing a plurality of program loops having a corresponding plurality of program voltages associated therewith. A first one of the plurality of program loops is activated to generate a first program voltage to program a first one of the plurality of memory cells. A second one of the plurality of program loops is activated to generate a second program voltage to program a second one of the plurality of memory cells.