Patents Represented by Attorney N. Rhys Merrett
  • Patent number: 5861798
    Abstract: An electrical noise generation circuit for use in conjunction with an electro-acoustic transducer to simulate the sound of burning wood. A small loudspeaker enclosure accommodates a battery driven circuit in which a wideband electrical noise signal is produced by current flow through a zener diode. The noise signal is amplified by a frequency selective amplifier designed to have a high gain at a selected frequency in the audio frequency range, and rectified to produce unipolar signals which have randomly variable amplitudes and occur at random intervals. The unipolar signals are amplified by an amplifier having an adjustable input threshold bias. By adjustment of the bias level, output signals from the amplifier, and sounds produced by the loudspeaker, may be varied from intermittent individual pulses to rapid "bursts" of pulses. Operation of the circuit in proximity to an artificial log fire produces a surprisingly realistic audible simulation of wood burning sounds.
    Type: Grant
    Filed: March 6, 1997
    Date of Patent: January 19, 1999
    Assignee: DEA Mfg.
    Inventor: Ernest T. Ankele, Jr.
  • Patent number: 5596766
    Abstract: A programmable logic device (PLD) and configurable logic network in which one or more logic combination networks (LCN) each receives logic inputs from two or more PLDs (PLD1, PLD2) and generates logic outputs (O, P) which provide inputs to programmable selectors (POR, UCL, . . . ) for controlling implementation of logic functions of various types and functionality by a controllable logic function sub-network by routing through the sub-network, logic values and logic instructions originating externally of the PLD's. Each programmable logic device includes an AND logic array (FAND . . . ) having inputs for receiving signals (Ax, Bx) and generating product term output signals and an OR logic array (OG . . . ) having inputs for receiving signals and generating sum term output signals (OF . . . ).
    Type: Grant
    Filed: February 16, 1995
    Date of Patent: January 21, 1997
    Assignee: Infinite Technology Corporation
    Inventors: Earle W. Jennings, III, George H. Landers
  • Patent number: 5568803
    Abstract: A gaseous fuel burner assembly for heating a space particularly an oven of a domestic cooking appliance comprises a gaseous fuel burner separated from the space by a baffle plate, and, also separated from the space by the baffle plate, a fan for withdrawing air from the space via an aperture or apertures in the plate and returning that air to the space via an exit or exits adjacent the edge of the plate, the or each aperture being so located that, during its passage from the aperture or apertures to the exit or exits, the air passes close to the burner. The fan may also draw in air from a plenum chamber behind the oven. The burner may be of the duplex variety and may have two independently controllable burner heads.
    Type: Grant
    Filed: April 4, 1995
    Date of Patent: October 29, 1996
    Inventor: Geoffrey J. E. Brown
  • Patent number: 5192400
    Abstract: Solar cells are formed of semi-conductor spheres of P-type interior having an N-type skin are pressed between a pair of aluminum foil members forming the electrical contacts to the P-type and N-type regions. The aluminum foils, which comprise 1.0% silicon by weight, are flexible and electrically insulated from one another. The spheres are patterned in a foil matrix forming a cell. Multiple cells can be interconnected to form a module of solar cell elements for converting sun light into electricity.
    Type: Grant
    Filed: July 31, 1989
    Date of Patent: March 9, 1993
    Assignee: Texas Instruments Incorporated
    Inventors: Sidney G. Parker, Milfred D. Hammerbacher, Jules D. Levine, Gregory B. Hotchkiss
  • Patent number: 5175488
    Abstract: A master bias voltage regulator circuit (5) has an output node for supplying a temperature compensated reference voltage (VREF1) to an input node of at least one slave ECL bias regulator circuit (4). The temperature compensated reference voltage is also compensated for a temperature-related characteristic of at least one ECL load, such as an ECL gate (2), and is also compensated for a temperature-related characteristic of the at least one slave ECL bias regulator circuit. VREF1 is sourced from an emitter of an output transistor (5Q7) and the collector of the output transistor is coupled to the emitter of a matching transistor. This technique is shown to provide improvements, relative to the prior art, in output reference voltage stability over variations in power supply voltage, temperature and process variations, while also reducing power consumption.
    Type: Grant
    Filed: May 10, 1991
    Date of Patent: December 29, 1992
    Assignee: Digital Equipment Corporation
    Inventor: Andrew P. Moroney
  • Patent number: 5148338
    Abstract: A disk drive for magnetic data storage media includes a spindle bearing arrangement having a rotatable portion surrounding and mounted by bearings on a stationary portion. A spindle hub having a cylindrical outer surface and a concentric interior cavity is rigidly attached to the rotatable portion of the spindle bearing arrangement. The cylindrical outer surface of the spindle hub provides a mounting surface for a stack of storage disks. A brushless direct current motor is mounted within the hub cavity. The rotor of the motor includes a sleeve rigidly attached to the floor of the spindle hub cavity and providing a return flux path for the motor. The spindle hub and the sleeve have distinct coefficients of thermal expansion and a radial spacing between the sleeve and the spindle hub allows for unconstrained thermal expansion of the sleeve and the spindle hub. The hub cavity floor incorporates a concentric annulus for accurate centering of the sleeve within the cavity.
    Type: Grant
    Filed: November 14, 1990
    Date of Patent: September 15, 1992
    Assignee: Digital Equipment Corporation
    Inventor: Tave J. Fruge
  • Patent number: 5110410
    Abstract: A procedure for planarizing a group II-VI composition which includes a resist and etch-back procedure wherein a thick resist coating relative to the degree of non-planarity is spun over a non-planar group II-VI layer to provide a planar resist surface. The resist is then etched back to the group II-VI layer with etching of both the resist and the group II-VI layer then continuing simultaneously and at substantially the same etch rate until all of the resist has been removed. The etching takes place in a chamber having a parallel plate RF plasma etcher using a dry etchant which uses the RF plasma. The etchant is a hydrogen and oxygen combination at low pressure which is activated by the RF excitation. An inert gas, preferably argon, and methane can optionally be added to the gas flow. The flow rate at each inlet is continuously adjustable. The flow of gas into the chamber continues while the chamber is also being pumped simultaneously to maintain the desired pressure within the chamber.
    Type: Grant
    Filed: August 13, 1990
    Date of Patent: May 5, 1992
    Assignee: Texas Instruments Incorporated
    Inventor: Jerry L. Elkind
  • Patent number: 5111260
    Abstract: Field effect transistors in which the channel region is made of thin highly doped polysilicon which is preferably also hydrogen passivated.
    Type: Grant
    Filed: July 5, 1990
    Date of Patent: May 5, 1992
    Assignee: Texax Instruments Incorporated
    Inventors: Satwinder Malhi, Rajiv Shah
  • Patent number: 5109351
    Abstract: Layered arrays of nearest-neighbor connected computation cells plus an error computation layer provide a learning network.
    Type: Grant
    Filed: August 21, 1989
    Date of Patent: April 28, 1992
    Assignee: Texas Instruments Incorporated
    Inventor: L. Ray Simar, Jr.
  • Patent number: 5106777
    Abstract: A method of forming a trench in a semiconductor body is disclosed herein. A field oxide 16 is grown over a portion of n-well 8 where trench 26 is to be formed. Nitride layer 20 and TEOS oxide layer 22 are deposited. Resist 24 is patterned and TEOS layer 22, nitride layer 20, and field oxide layer 16 are etched. Resist 24 is removed and trench 26 is etched through n-well 8 and into substrate 4. Thin oxide 28 is then grown on the sidewalls of trench 26. Polysilicon is deposited into trench 26 and etched back to form polysilicon plug 30 . Sidewall oxide 32, to prevent voids in the topography of trench 26, is formed on top of polysilicon plug 30 along the outer edges of trench 26. To prevent leakage into trench 26, a thick thermal oxide cap 34 is grown over trench 26.
    Type: Grant
    Filed: September 27, 1989
    Date of Patent: April 21, 1992
    Assignee: Texas Instruments Incorporated
    Inventor: Mark S. Rodder
  • Patent number: 5103113
    Abstract: A driving circuit for providing a predetermined voltage as a driving signal to a respective word line in a dynamic random access memory in a short time. The driving circuit includes an operation signal supply circuit portion for providing an operation signal, a driving signal output circuit portion which receives the operation signal and provides a driving signal as an output, and a voltage supply circuit portion for providing a predetermined voltage to the driving signal output circuit portion in producing the driving signal. A bipolar switching element is provided in the driving signal output circuit portion to control the voltage supply from the voltage supply circuit portion and responds to the operation signal to provide the voltage from the voltage supply circuit portion as the voltage producing the driving signal in a short time.
    Type: Grant
    Filed: June 13, 1990
    Date of Patent: April 7, 1992
    Assignee: Texas Instruments Incorporated
    Inventors: Takashi Inui, Shunichi Sukegawa
  • Patent number: 5101261
    Abstract: An electronic circuit device wherein lines are provided to connect elements, and wherein a plurality of island shaped non-line parts, which do not have the function of the lines, are formed along the length of the lines.
    Type: Grant
    Filed: November 14, 1990
    Date of Patent: March 31, 1992
    Assignee: Texas Instruments Incorporated
    Inventor: Takayuki Maeda
  • Patent number: 5094973
    Abstract: A T-shaped trench intersection shaped to make uniform the wall-to-wall spacing at the trench intersection and prevent the formation of voids when the trench is filled with a conformal insulating material.
    Type: Grant
    Filed: June 21, 1990
    Date of Patent: March 10, 1992
    Assignee: Texas Instrument Incorporated
    Inventor: Harry F. Pang
  • Patent number: 5094936
    Abstract: A process for silylation of positive or negative photosensitive resist layer on a semiconductor wafer after the resist layer has been exposed to radiant energy through a mask which includes introducing a silylating agent to the wafer at high pressure over 760 torr and, usually, at temperatures less than 180.degree. C. Increased pressure increases the rate of silylation, allows practical use of lower process temperatures, and, therefore, allows better process control. Also an apparatus is disclosed for applying the high pressure silylation process to a wafer.
    Type: Grant
    Filed: June 26, 1990
    Date of Patent: March 10, 1992
    Assignee: Texas Instruments Incorporated
    Inventors: George R. Misium, Cesar M. Garza, Cecil J. Davis
  • Patent number: 5091783
    Abstract: A television receiving system includes a digital unit, which has at least one single-instruction multiple-data processor, especially suitable for television processing. The processor receives data samples fo each horizontal line word-serially, but processes the line in parallel. The processor has input, computational, and output layers that operate concurrently. Internal register files emulate line memory to eliminate the need for external line memories. The processor may be programmed with various improved definition television tasks, downloaded to it from a host development system. Field memories and multiplexers control the data flow so that a still picture may be displayed.
    Type: Grant
    Filed: March 1, 1990
    Date of Patent: February 25, 1992
    Assignee: Texas Instruments Incorporated
    Inventor: Hiroshi Miyaguchi
  • Patent number: 5091759
    Abstract: A heterostructure field effect transistor having a buffer layer comprising a first compound semiconductor material. A layer of second semiconductor material different from the first material is formed over the buffer layer. The second layer has a total thickness less than 250 .ANG.. A doped third semiconductor layer formed over the second layer. The net has a dopant concentration in the second layer is greater than the net dopant concentration in the third layer. A gate layer is positioned over the third layer. In a preferred embodiment the second layer is a pulse-doped pseudeomorphic material. There is also provided a method for making the heterostructure field effect transistor. A doped pseudomorphic semiconductor layer of a first conductivity type is formed between first and second other semiconductor layers, the second layer including a net dopant concentration of the first conductivity type. A Schottky gate electrode is formed in contact with the second layer.
    Type: Grant
    Filed: November 26, 1990
    Date of Patent: February 25, 1992
    Assignee: Texas Instruments Incorporated
    Inventors: Hung-Dah Shih, Bumman Kim
  • Patent number: 5084409
    Abstract: Shadow masking layer (130) is undercut during etch of sidewall layer (120) thus preventing sidewall growth during growth of heteroepitaxial region (140), resulting in a planar structure with a high integrity of crystal in the grown region (140).
    Type: Grant
    Filed: June 26, 1990
    Date of Patent: January 28, 1992
    Assignee: Texas Instruments Incorporated
    Inventors: Edward A. Beam, III, Yung-Chung Kao
  • Patent number: 5082522
    Abstract: Preferred embodiments mask select regions of a circuit surface (141) prior to abrading the surface with diamond particles to form nucleation sites (200). The mask (150) is then removed prior to forming a diamond layer (160). Diamond layer (160) grows on the surface except in those regions wherein the mask (150) prevented the formation of nucleation sites (200).
    Type: Grant
    Filed: August 14, 1990
    Date of Patent: January 21, 1992
    Assignee: Texas Instruments Incorporated
    Inventors: Andrew J. Purdes, Francis G. Celii
  • Patent number: 5083187
    Abstract: An integrated circuit device is disclosed. In one embodiment, the device has a semiconductor chip having an electrical circuit that is connected to a bonding pad. A metal layer overlies the bonding pad, and a metal bump is connected to the metal layer. The metal bump receives power for the electrical circuit. The method of manufacture allows a designer to form a power supply bus in the metal layer. The metal layer may lie over an active circuit of the semiconductor chip.
    Type: Grant
    Filed: April 16, 1991
    Date of Patent: January 21, 1992
    Assignee: Texas Instruments Incorporated
    Inventors: Michael A. Lamson, Darvin R. Edwards
  • Patent number: 5081069
    Abstract: Method and apparatus are disclosed for depositing a uniform layer of material, such as titanium dioxide, on the surface of an object, such as a silicon sphere of a solar array (7). Component gases are injected at predetermined rates into a heated reaction chamber (5) where they react. Because of the reaction rate and injection velocities of the gases, the reaction is substantially completed at a calculated location inside the reaction chamber (5). The object which is to receive the layer, such as the solar array (7), is placed at the calculated location in the reaction chamber (5). The platform (68) to which the solar array (7) is attached is simultaneously tilted and rotated such that all areas of the surface of the array (7) are uniformly exposed to the titanium dioxide reactant.
    Type: Grant
    Filed: December 26, 1989
    Date of Patent: January 14, 1992
    Assignee: Texas Instruments Incorporated
    Inventors: Sidney G. Parker, Jerry Wood, Robert T. Turner, Craig A. Fischer