Abstract: A push-pull output stage of an integrated circuit for generating a pulse-like output signal in dependence upon a pulse-like input signal. The push-pull output stage includes complementary output field-effect transistors which are formed by respective first and second groups of parallel-connected subtransistors (P1 to P4; N1 to N4), the subtransistors in each group being of the same conductivity type and opposite from that of the subtransistors in the other group. A resistance element (TP0 to TP3; TN0 to TN3) is connected into the lead to each gate electrode of each of the subtransistors (P1 to P4; N1 to N4) of the two groups of subtransistors. A disconnecting field-effect transistor (PD1 to PD4; ND1 to ND4) is associated with each subtransistor (P1 to P4; N1 to N4) of the two groups of subtransistors.

Abstract: A method of passivation of Hg.sub.1-x Cd.sub.x Te and similar semiconductors by surface oxidation (such as anodic) followed by chemical conversion of the oxide to either sulfide or selenide or a combination of both is disclosed. Preferred embodiments provide sulfide conversion by immersion of the oxide coated Hg.sub.1-x Cd.sub.x Te in a sodium sulfide solution in water with optional ethylene glycol and the selenidization by immersion in a solution of sodium selenide plus sodium hydroxide in water and ethylene glycol. Also, infrared detectors incorporating such sulfide and selenide passivated Hg.sub.1-x Cd.sub.x Te are disclosed.

Abstract: A push-pull output stage of an integrated circuit for generating a pulse-like output signal in dependence upon a pulse-like input signal. The integrated circuit of which the push-pull output stage is a part is susceptible to high switching speeds in which the pulse-like signal varies between high and low voltage levels. The push-pull output stage inhibits the overshoot of the pulse-like signal leading to inaccurate interpretation of the pulse-like signal as having a high voltage level when the pulse-like signal actually has a low voltage level. The output stage includes output field-effect transistors comprising two groups (12, 14) of parallel-connected subtransistors (TN1 to TNn, TP1 to TPn). The gate zones of the subtransistors in each respective group are connected together. To the gate zones of the subtransistors (TN1 to TNn) of at least one (12) of the two groups (12, 14) a current dissipating or grounding transistor (TS1) is connected.

Abstract: The disclosure relates to a circuit to reduce the gate loss in a semiconductor travelling wave power amplifier using series capacitors on the gate feeding lines for a distributed amplifier design. The circuit arrangement significantly increases the gate width of the amplifier with a resultant increases of the broadband output power and efficiency.

Abstract: A three step annealing treatment for Hg.sub.1-x Cd.sub.x Te includes a high temperature anneal to reduce excess tellurium, followed by an intermediate temperature anneal to reduce the supersaturation of metal vacancies, and lastly a low temperature anneal to reduce metal vacancies; see FIG. 4. The intermediate anneal reduces the metal vacancy concentration sufficiently that microvoids do not form from condensation of metal vacancies in desired portions of the Hg.sub.1-x Cd.sub.x Te during the low temperature anneal. Alternate preferred embodiments include more than three steps and incremental cooling.

Abstract: A read/write configuration (44) is provided for switching signals between a source (46) and either a single output (60) or a plurality of outputs (60) and (62). A control circuit (68) operates to control a signal switching circuit (64) and a power supply switching circuit (66) in response to a control signal input thereto. More particularly, in a reading mode, the switches within signal switching circuit (64) are opened while the switch within power supply switching circuit (66) is closed. Further, in a writing mode, the switches within signal switching circuit (64) are closed while the switch within power supply switching circuit (66) is opened.

Abstract: A damping circuit is described for the antenna resonance circuit (28) of a radio transmitter-receiver (10) which in a transmitting phase transmits a time-limited high-energy interrogation pulse and in a receiving phase following the transmitting phase is ready to receive high-frequency response signals coming from a responder (26) which transmits said response signals as reaction to the reception of the interrogation pulse. In the damping circuit (24) a damping member (R5, R5, R6) is provided which is adapted to be connected to the antenna resonance circuit and disconnected therefrom. A switching means (T4, T5) on receiving a switching voltage applies the damping member (R4, R5, R6) to the antenna resonance circuit (28).

Abstract: Heat activated method for developing and improving the definition of a patterned heat-photoresist layer as applied to a substrate surface of different material, such as a semiconductor slice, in the fabrication of an electronic structure or photomask, through the use of a reactive species of oxygen including monatomic oxygen or ozone in an oxygen-containing gas. A layer of photoresist material upon being selectively exposed to an energy source, such as ultraviolet radiation, X-ray, or E-beam radiation acquires a predetermined patterned definition therein because of chemical changes in the photoresist material which is photosensitive. After such selective exposure, the photoresist layer is characterized by a differential reactivity which is heightened by a chemical or a physical change occurring in either one of the exposed or unexposed portions of the layer of photoresist material enabling the selective removal thereof.

Abstract: A machine has been developed for photoresist processing which has two filtered upward flowing baths, one for the develop fluid and one for the rinse fluid. In order to be able to develop photoresist patterns with submicron geometries, it is necessary to retreat from the current method of developing on a conventional spin developer. The batch immersion develop would suffice in certain applications, but contamination and automation obstacles cannot be overcome with the batch immersion process. Also, the develop process cannot be accomplished on very small geometries which developing pattern side up due to ununiform developing across the wafer causing critical dimension sizing problems. The described concept utilized an upside down immersion process with automated in line capabilities. It requires a filtered bubble free, temperature controlled, slow upward flowing develop chemical which the wafer is immersed into while spinning very slowly.

Abstract: A three dimensional package having at least one semiconductor chip having input/output conductive pads along its periphery includes a dielectric carrier over at least a portion of the chip and a plurality of conductors mounted on the carrier between the chip and the dielectric carrier. The plurality of conductors are mounted within the periphery of the chip with one end connected to the conductive pads and with the other end of the plurality of conductors exiting from the same side of the chip. The plurality of conductors exiting from the same side are electrically coupled to an interconnect substrate.

Abstract: An apparatus (10) for real-time in-line monitoring of a material (26) comprises a blackbody source (12), a first set of reflective surfaces (17) and a second set of reflective surfaces (38). Electromagnetic radiation (16) is emitted from the blackbody source (12) into the first set of reflective surfaces (17), which directs the radiation to a flow stream or material (26) which is to be tested. The radiation passes through or is reflected from the material (26). A transmission spectrum, resulting from the passage of the radiation through the material (26) or the reflection from the material (26), is then received by the second set of reflective surfaces (38). The second set of reflective surfaces (38) diffracts the transmission spectrum (34-36) and focusses the diffracted spectrum onto a detector (52). The detector (52) provides transmission spectrum data to a microprocessor (58) for comparison to a characteristic spectrum of the material (26) for determination of the necessity of a process adjustment.

Abstract: An insulated-gate field-effect transistor device characterized by the channel region consisting of the intermediate heavily doped portion (50; 72) and two lightly doped portions (46, 48; 74,76) provided on both sides of the heavily doped portion. Such a field-effect transistor device is advantageous in that it provides a surface potential locally increased to act as an energy barrier to minority carriers. This permits control over the threshold voltage of a MOS transistor or over the punch-through current of a punch-through transistor without having recourse to the use of a high carrier density throughout the channel region. The carrier density of the channel region being rather reduced, not only reduction in leakage current but improvement in withstand voltage characteristics can be achieved in a device according to the present invention.

Abstract: Digital-analog converter intended to convert into analog signals digital signals formed of sign bits, of step bits and of segment bits, particularly signals coded by data compression according to law A, the said converter comprising a sign generator (4), intended to receive the sign bit of the said digital signal, a step generator (7), connected to the output of the sign generator and intended to receive the step bits of the said digital signal and to a segment generator (8) connected to the step generator and intended to receive the segment bits of the said digital signal, characterized in that the segment generator (8) is connected to the sign generator by means of the step generator (7) only.

Abstract: This invention relates to a semiconductor integrated circuit device which has an insulated-gate type element part comprising a capacitor which is formed through the use of a trench in a semiconductor layer, wherein a low-resistance buried layer is formed in the semiconductor layer prior to forming the trench so that the trench is formed to be surrounded by the low-resistance buried layer and thereby the low-resistance buried layer is used as an electrode of the capacitor.

Abstract: An apparatus for wet etching of thin films with which etching rate differences as between various regions of a respective thin film down to only 5% can be achieved. The apparatus includes a housing (10) providing a liquid treatment chamber in which at least one rotational-symmetrical basket (12; 14) is arranged for accommodating semiconductor slices (16) having the thin films to be etched. The basket (12, 14) rests on two rollers (18, 20; 22), one of which is driven. Longitudinally above the basket (12; 14), flat jet nozzles (24) are arranged in such a manner that the jets of etching solution sprayed out of the nozzles form a homogeneous flat jet (26). The flat jet (26) is directed laterally in the direction of the axis of symmetry of the basket (12; 14). With this apparatus, overflow conditions on the surfaces of the slices (16) to be processed are obtained which are so uniform that the apparatus is suitable for use in the wet etching of aluminium layers in device fabrication.

Abstract: A method for forming a self-aligned horizontal transistor includes the step of first defining a narrow base contact on an isolated N-tank (10) to define a first reference edge (41). A layer of sidewall oxide (40) is then disposed on the vertical wall of the base contact (34) to define a second reference edge (42). An emitter well (44) and a collector well (46) are then defined on either side of the contact with the vertical wall of the emitter well (44) aligned with the reference edge (42). A dopant material is then disposed adjacent the reference edge (42) and the dopant diffused into the substrate from a lateral direction to form a P-type base region (58) with a graded impurity profile. N-doped regions (64) and (66) are then formed in the emitter and collector wells to form the emitter and collector of the transistor.

Abstract: An optical switching device having an organic thin film selectively enabling optical transmission and cut-off of infrared light of a predetermined wavelength by changing applied potential.

Abstract: Input circuit having an input terminal for accepting an input signal varying between "high" and "low" voltage magnitudes, wherein the input circuit is provided with a compensated threshold voltage located between the "high" and "low" voltage magnitudes for properly characterizing the status of the input signal depending upon whether the input signal has a voltage above or below the threshold voltage. The input circuit has a load circuit disposed between a power supply side and an input stage of the input circuit. The load circuit includes a logic element and operates to temporarily increase the threshold voltage associated with the input stage in response to noise generated at the ground side of the input circuit, thereby preventing the noise level from surpassing the threshold voltage as temporarily increased.

Abstract: A fuse link (50) is formed using a method which offers greater scalability of the general conductor system used to wire the device. An oxide mask (36) having the shape of a desired fuse link is formed over a thin metallization layer (34). A barrier layer (38) is formed over the thin metallization layer (34). A conductive layer (40) is formed over the barrier layer (38). A photoresist mask (42) supplied to the conductive layer (40), and the conductive layer is etched to formed interconnects (44, 46). Subsequently, the barrier layer (38) and thin metallization layer (34) are etched, thus rendering a fuse link (50) between interconnects (44, 46) under the oxide mask (36).

Abstract: Selective growth of GaAs and related semiconductors (34) by use of tungsten silicide and related materials for growth masks (36) plus devices incorporating the selective growth plus use of the growth masks as electrical contacts are disclosed. The deposition of semiconductor (38) on such masks (36) is inhibited and single crystal vertical structures (34) grow on unmasked regions of the lattice-matched substrate (32). Variation of the mask (36) composition can vary the inhibited deposition on the mask (36) from small isolated islands of polycrystalline semiconductor (38) to a uniform layer of polycrystalline semiconductor abutting the single crystal structures. Preferred embodiments include bipolar transistors with the selectivity grown structure forming the base and emitter or collector and the mask being the base contact and also include lasers with the vertical structures including the resonant cavities with the mirros being the sidewalls of the vertical structures.