Abstract: An on-chip power supply regulation system for a VLSI circuit such as a dynamic RAM is disclosed. The system includes a high power supply voltage detection circuit and a power supply clamp circuit, where a clamped voltage generated by the clamp circuit biases the functional circuitry when the high power supply voltage detection circuit detects an overvoltage conditions. The bias voltage applied to the functional circuitry in the normal operating condition can be a regulated voltage generated from the power supply voltage. Further included in the disclosed circuit is a burn-in voltage generation circuit and a burn-in voltage detection circuit, which can apply an accelerated voltage which depends upon the applied power supply voltage, when the power supply voltage is higher than during normal operation but lower than in the overvoltage condition enabling the clamp operation.

Abstract: The disclosure relates to the article and a method of forming a field oxide which extends over an isolation trench and the adjacent substrate wherein a portion of the trench insulating sidewall at the top region thereof is removed and replaced by polysilicon. The exposed silicon on the substrate and adjacent polysilicon are than oxidized to form the field oxide which is continuous, disposed above and contacts the remaining sidewall insulator in the trench.

Abstract: A tunneling device (50) with the emitter (62) to collector (58) current transported by resonant tunneling through a quantum well (52) and controlled by carriers injected into the well (52) from a base (60) is disclosed. The injected carriers occupy a first energy level in the well (52) and the resonant tunneling is thorough a second energy level in the well (52) thereby separating the controlled carriers from the controlling carriers. AnotherThree-terminal tunneling devices using three different bandgap semiconductor materials to segregate controlling carriers from controlled carriers are disclosed.

Abstract: A CMOS output buffer is disclosed, which provides ESD protection by incorporating a low resistance path within the p-channel pull-up device. Output buffers according to the prior art can be damaged by ESD occurring at the output terminal having a positive polarity, as the drain-to-substrate diode of the pull-down transistor breaks down in the reverse-bias direction, especially when second breakdown occurs. The p-channel pull-up device, formed within an n-well, is fabricated to have n-type diffusions disposed near to the p-type drain diffusions. The distance between the n-type diffusion and the drain diffusions in the pull-up device reduces the series "on" resistance of the drain-to-n-well diode of the pull-up device, to a level which keeps the voltage at the output terminal below the reverse-bias breakdown voltage of the drain-to-substrate diode in the pull-down device. The pull-up device may be constructed in a ladder structure to facillitate the reduction of this resistance.

Abstract: In order to compare the total reached by a counter counting pulses from a source with a given number, the more significant digits from the counter are compared with the corresponding digits of the given number. The comparator produces an output when the groups of more significant digits are equal. An adjusted output taking account of the less significant digits of the given number is obtained by delaying the output by a time period equal to that required for the number of pulses from the source to be incremented by the number represented by the less significant digits of the given number. The time delay is provided by a multi-stage shift register using the pulses from the source as shift pulses, the output from the comparator being applied to the first stage and the adjusted output being derived from a stage selected according to the less significant digits of the given number.

Abstract: The invention provides an integrated circuit capacitor with a silicided polysilicon electrode (which silicide has not been used as an etch stop) as a bottom plate and a metal layer as a top plate. Subsequent to the formation of a patterned polysilicon layer, a multilevel dielectric is formed, and a via is etched therethrough to a polysilicon capacitor bottom plate. Then the polysilicon bottom plate is clad with a refractory metal silicide. The capacitor dielectric is then deposited, such a dielectric preferably consisting of an oxide/nitride layered dielectric. Contacts are etched to diffusion and to polysilicon electrodes as desired, and metal is deposited and patterned to form the top electrode of the capacitor over the capacitor dielectric, and to make contact as desired to diffusion and to polysilicon. This provides an improved silicide layer in the capacitor, as compared to processes which etch through oxide down to the silicide, and thus are using the silicide as an etch stop.

Abstract: The described embodiments of the present invention provide a memory cell and method for fabricating that memory cell and memory array including the cell. The memory cell is a trench capacitor type having a transistor (1-1-2) formed on the surface of a major face of a substrate (16) and having a capacitor (2-1-2) formed in the substrate around the periphery of a trench. The capacitor and transistor are connected by a buried, heavily doped region (26) having the opposite conductivity type from the substrate. A doped storage area (24) having the same doping type as the buried doped region surrounds the trench. A field plate (30) is formed in the trench separated from the storage region by a dielectric layer (32). The field plate extends onto the isolation areas between memory cells thus providing isolation between cells using a minimum of surface area.

Abstract: Data selector circuit including a plurality of data registers connected in parallel via corresponding output buffers to a plurality of output drivers, wherein a decoder and selector portion is interposed between the output buffers and the output drivers for selectively providing one of a plurality of serial data output sequences from the data registers to the output drivers rather than a parallel data output format from the plurality of data registers which would otherwise occur. The decoder and selector portion is controlled by a partial address buffer which is provided with serial sequence selection data.

Abstract: Vertical buried emitter heterojunction bipolar transistors having greatly reduced emitter to base junction area and collector dimensions are fabricated in a gallium arsenide substrate to form an integrated circuit structure. The ability to scale these critical dimensions is made possible by forming a portion of the base along the side walls and bottom of a trench which has been etched in the upper two layers of a layered gallium arsenide structure. The base is formed by implanting beryllium into the surface of an upper layer, the trench sidewalls which are formed in an undoped layer, and the bottom of the trench which is an undoped layer formed on the buried emitter. A GaAs collector layer having reduced lateral dimensions is deposited in the trench and in part, on the surface of the layered structure. Since only a small portion of the base region (the bottom of the trench) is in direct contact with the heavily doped emitter layer, the emitter to base junction area can be significantly reduced.

Abstract: A speaker verification system receives input speech from a speaker of unknown identity. The speech undergoes linear predictive coding (LPC) analysis and transformation to maximize separability between true speakers and impostors when compared to reference speech parameters which have been similarly transformed. The transformation incorporated a "inter-class" covariance matrix of successful impostors within a database.

Abstract: The invention provides a bipolar transistor structure on a buried oxide layer for use in an integrated circuit and a method for fabricating the same. The invention may be incorporated into a method for fabricating bipolar transistors in a BiCMOS structure. The bipolar transistor is constructed in two stacked epitaxial layers. The first epitaxial layer is used to form both the MOSFET and the buried collector of the bipolar transistor. The second epitaxial layer is grown as a blanket epitaxial layer. The intrinsic collector and the base of the bipolar transistor are formed in the second epitaxial layer. An oxide layer is formed over the base. The emitter is formed of a polysilicon layer which is deposited through an opening in the oxide layer such that the polysilicon layer contacts the second epitaxial layer.

Abstract: A dynamic read/write memory cell array employs stacked capacitors consisting of three levels of conductor separated by dielectric material. In one embodiment, the central level is a common plane, and the upper and lower levels are connected to the source regions of the pair of access transistors of two adjacent cells. In this manner, capacitors for adjacent cells occupy the same area, almost doubling the capacitor value per unit area.

Abstract: A transistor (42) is provided having a gate conductor (44) formed adjacent a semiconductor substrate (46) and separated therefrom by a gate insulator (48). Sidewall spacers (52, 54) are formed at the sides of gate conductor (44) and adjacent semiconductor substrate (46). Diffused regions (56, 58) are formed within semiconductor substrate (46) in order to provide source/drain regions for transistor (42). Positive charges from radiation are trapped within sidewall spacers (52, 54) thereby attracting negative charges from semiconductor substrate (46) such that a negative charge layer is created between diffused region (56) and gate edge (50a) and also between diffused region (58) and gate edge (50b).

Abstract: Monolithic gallium arsenide limiters (30) formed of p-i-n diodes (32, 34) that are distributed devices between conductors of coplanar waveguide sections (40, 42, 44) are disclosed. The diode doped regions underlie the coplanar conductors and the diode intrinsic region underlies the coplanar waveguide gap. The grounded coplanar segments connect to a backside ground through vias (74).

Abstract: A TTL gate (22) includes a current generating circuit (24) comprising an NPN transistor (30) having its base coupled to a diode (24) and its emitter coupled to one of the gate's output transistors (14). Transistor (30) enables diode (24) to deliver a high current of short duration to the output OUT responsive to a low-to-high output transition. The current provides low-to-high output transition while protecting output transistor (14) from damaging currents caused by a short circuit at output OUT.

Abstract: The disclosure relates to oxide-semiconductor interfaces which are grown with varying amounts of fixed positive (or negative) charge. The invention utilizes these different values to form a channel stop for a charge transfer device. For HgCdTe two different oxides are used, namely, those produced by wet anodization (having large values of fixed positive charge) and plasma oxidation (having low values of fixed charge). The voltage range of operation of the active gate is determined by the difference in fixed positive charge for these regions and the insulator thicknesses.

Abstract: A three dimensional display wherein a scanned light beam is displayed upon a rotating display member rotating about a fixed axis for receiving and displaying the scanned light beam on a first surface thereof, fixed points in the display impinging upon the display member to display a harmonic motion along an axis passing through the scanned light beam in response to rotation of the display means. In accordance with a second embodiment of the invention, the display member is translucent and a second scanned light beam is displayed upon an opposing surface of the display member for receiving and displaying the second scanned light beam on the opposing surface thereof to display a harmonic motion along an axis passing through the second scanned light beam in response to rotation of the display means.

Abstract: This interpolative filter comprising N differentiating stages (4A-4N) constituting a section of low sampling frequency and N integrating stages (5A-5N) constituting a section of high sampling frequency is characterized in that is further comprises modulators (7A-7N) which are inserted into the string of integrators and which are intended to eliminate the increasing of the number of bits of the signal at each integration stage, and in that the said integrators are each included in a differentiation loop.

Abstract: A dual-port memory which features a pipelined serial port is disclosed. The serial side of the dual-port memory contains a ripple counter which is broken between predetermined stages. The contents of the stages above the break are decoded to select a group of bits of the serial register for output, and the contents latched in a latch. In serial output, the contents of the stages below the break are decoded, so that responsive to the stages below the break reaching a certain value, the stages above the break are incremented and the incremented value decoded. Pass transistors between the register and the latch are turned off during such time as the incremented value is being decoded, so that the new value will not disturb the output. The latched output is selectively presented by a multiplexer which selects the latch bits responsive to the value of the stages below the break. Upon the value of the stages reaching its minimum value (i.e.

Abstract: Thyristors of one conductivity type formed as an array in a first semiconductor body are respectively connected in parallel with thyristors of the opposite conductivity type formed as an array in a second semiconductor body to produce an array of triacs. In each body the thyristors are separate except for a common anode or cathode region and terminal connection, and are formed in an epitaxial layer divided by PN junction isolation regions on a substrate of opposite conductivity type. The thyristors may be constructed to be triggered by gating signals of either polarity.