Abstract: A memory system includes a plurality of memory controllers which connect to a common bus. Each memory controller includes reconfiguration apparatus which enables the controller when faulty to be switched off line and another controller to be substituted in its place so as to maintain system memory contiguous.

Abstract: A step motor driving circuit, wherein the motor has two pairs of magnetically coupled windings (1, 2 and 3, 4) and includes switching transistors (9, 10, 11, 12) associated to the windings, diodes (15, 16, 17, 18) in parallel to the switching transistors for the recycle of the current induced during the possible current chopping and the phase switching, and a diode (6-8) and a capacitor (5-7), in parallel to each other and series connected between the voltage source, and each pair of magnetically coupled windings. When a phase is de-energized, the driving circuit allows the recovery of the energy stored in such phase by charging the capacitor coupled to it. From such capacitor the energy is then returned to the phase magnetically coupled to the previous one in case of phase switching or to the same phase in case of current chopping. The driving circuit speeds up the phase switching and therefore increases the torque delivered by the motor at high frequencies.

Abstract: Serial printer provided with cutter, the printer being of the type in which printing is performed by a printing head mounted on a carriage sliding on guides parallel to the printing line and a continuous printing support moves perpendicularly to the direction of such guides leaning against a substantially vertical platen. A rotating cutter is lever-mounted on the carriage over the printing head in a position very close to the printing line and it can be actuated in order to partially overlap a cutting edge of the platen, the edge being parallel to the printing line.Owing to the printing head movement along the printing line, the rotating cutter when actuated operates the transversal cutting of the continuous form. The cut form is disposed in a collecting drawer behind the platen owing to the movement imposed by the rotating cutter and to the reduced thickness of the platen which constitutes a drawer wall.

Abstract: The apparatus displays information in a manner which permits viewing at convenient operator locations. It connects to a selected number of points within the computer printed circuit boards of the equipment. The apparatus includes light emitting diode circuits and associated transparent rods for conveying the light indicator information signals to convenient locations for operator viewing. The exposed ends of transparent rod elements are conically shaped so as to concentrate the light indicator signals in sharply defined cones of light so as to be viewed from any angle by an operator located at a considerable distance from the computer equipment.

Abstract: A common bus utilization detection logic that is used when a particular device connected to a common bus has been granted access to the common bus wherein bus access is granted on a priority basis. By positioning the bus utilization logic in priority positions on the common bus adjacent to the particular device whose bus use is to be detected, the bus utilization detection logic can determine when the common bus has been awarded to the particular device even though there may have been other devices simultaneously requesting access to the common bus. The bus utilization detection logic is used in a system analyzer connected to a data processing system having a common bus and permits the analyzer to be connected in the same manner as other devices are connected to the common bus. Also disclosed is a software analyzer and a data processing system having an asynchronous bus on which multiple words of data can be read from memory in response to a read request providing a starting memory address.

Abstract: A hand held tool for installing compression rings includes a pair of relatively reciprocable coaxial cylindrical independently spring biased elements housed within a cylindrical handle which includes mode control means automatically preconditioned for enabling the tool to perform either an installation or ejection operation. The mode control means includes a cylindrical radial cavity containing plural spring biased spherical ball detents and extends into corresponding portion of the outer reciprocable element. The positioning of a tapered central section of the inner reciprocable element coincides with the cavity so that one of the spherical ball detents normally sits within a hollow defined by the taper. When one spherical ball detent, in response to the mode control means being preconditioned by depressing a front end or shaft portion of the inner element, is positioned to lock the outer member to the handle, this allows the ring to be installed onto the cam shaped front end of the outer element.

Abstract: Keyboard coding apparatus couples to a plurality of keys and comprises a scanning interface including a counter (23), a decoder (13) and a multiplexer (22). The scanning interface, in response to each pulse received from a microprocessor (1) through an input lead (11), sends to the microprocessor on an output lead (10) a logic signal indicative of the state of any selected one of the keys. Whenever microprocessor 1 sends a pulse to the scanning interface, it increments by one the contents of an internal register and, before sending another pulse, processes the signal from the scanning interface. When the logic level of such signal indicates a condition of an actuated key, the microprocessor waits a predetermined time interval to establish that said selected key activation is valid, then waits until the selected key has been deactivated and then accesses the character code related to the actuated key from a memory location whose address is latched into its internal register.

Abstract: A data processing system which includes a central processing unit coupled over a common bus with a plurality of input/output controllers (IOCs) and main memory includes apparatus which allows an IOC to signal the CPU to wait and retry the current I/O instruction. Other apparatus is provided which enables the CPU to continually retry the I/O instruction until the IOC accepts or rejects the I/O instruction and which further allows the CPU to suspend the retrying of the I/O instruction and to process interrupt requests and data transfer requests from any one of the plurality of IOCs. After processing the interrupt or data transfer request, system control is returned to retrying the I/O instruction.

Abstract: In a data processing system having a plurality of units coupled for the transfer of information therebetween over a common electrical bus or for transferring information via a communication channel to other data processing systems during asynchronously generated information bus transfer cycles, an apparatus exists for reformatting data for transfer over the common electrical bus or via the communication channel. The apparatus is comprised of an eight-way multiplexer responsive to control bits for selecting one of eight different formats during write or read operations to or from a memory. Additionally, during read operations, the apparatus transfers a return address from a unit requesting information to the address bus so that data read from memory may be transferred to the requesting device. The formatting control bit is similarly reformatted from the data bus to the address bus bit.

Abstract: In a computer factory data collection terminal an electrical conduit enclosure for permitting wiring to be brought up through the conduit to the factory data collection terminal and for providing full wiring protection while still permitting the terminal to be installed or detached without opening the unit. A conduit enclosure having a base, cover, conduit fittings and special data and address signal connector and power connections is detachably mounted below the data collection terminal.

Abstract: A data processing system including a dual ported main memory that can be accessed by I/O controllers via a common bus or directly by the central processing unit. The main memory is comprised of a volatile RAM array that requires periodic refreshing to prevent loss of information. Access to the main memory is controlled by a priority resolver that awards access to the main memory on the basis of predetermined priority levels assigned to CPU, I/O and refresh requests. The priority resolver produces an early signal that is usable to initiate a memory cycle before the final winner of the main memory is determined. The logic path of the lowest priority requester is the shortest path thus allowing the lowest priority requester to initiate a memory cycle in the shortest amount of time even though another requester may ultimately win use of the memory. The priority resolver also provides for the early resetting of access requests so that subsequent requests can be made with minimum delay.

Abstract: A data processing system includes a microprogram controlled central processing unit that executes instructions. The instruction words include a data type field for identifying the type of operand processed during the execution of the instruction. The data type field signals and a number of control signals are applied to the address terminals of a read only memory. The read only memory output signals are tested by microwords of a microprogram to branch to firmware routines to process the operand type.

Abstract: An interactive terminal includes a central processor unit (CPU) having a microprocessor and a random access memory (RAM). Signals from the microprocessor place the RAM in a write protect mode. If the RAM receives a write instruction from the microprocessor when the RAM is in the write protect mode, then an illegal condition is indicated and a nonmaskable interrupt is generated to allow the terminal to recover. When the RAM is in the write protect mode, signals from the microprocessor restore the RAM to its normal read/write mode.

Abstract: A computer system which facilitates the execution of nested subroutines and interrupts is disclosed. As each branch transfer within the program is executed by a control area logic, a microcommand initiates the transfer of the return address, which has been derived from the address in the present routine, to a first register of a push down stack. In addition, the microcommand also pushes down one level the contents of all of the registers in the stack containing previously stored return addresses. Thus, a sequential return to unfinished routines or subroutines is provided. When the subroutine or hardware interrupt service routine is completed, a code in the address field enables the return address of the previously branched from or interrupted routine to be retrieved from the first register in the push down stack and to provide it as the address of the next instruction to be executed.

Abstract: An adjustable diameter pulley, particularly suitable for the belt tension adjustment in belt transmission system such as those used in serial printers, utilizing a central core having a tapered portion, a threaded cylindrical portion and also a plastic ring having external cylindrical surface and a central tapered opening. The opening receives the conical portion of the core and is provided with deep slits which allow its expansion. A second ring, screwed on the cylindrical portion of the core, causes the expansion of the plastic ring to vary.

Abstract: A data processing system includes a communication subsystem having an I/O microprocessor for communicating with a central processing unit and a main memory; and a line microprocessor for communicating with a number of devices. The I/O microprocessor and the line microprocessor communicate with each other through mailboxes stored in a shared memory. The line microprocessor interrupts the I/O microprocessor to process data bytes being transferred between main memory and a device requesting service when the line microprocessor has responded to the requesting device and loaded the mailbox.

Abstract: A hardware interrupt apparatus for assigning the microprogrammed control system to the highest priority hardware interrupt requesting service. In a microprogrammed control system having at least one hardware interrupt, the presence of a hardware interrupt request will cause the interruption of the currently executing microprogram at the end of the current microinstruction. The address of the next microinstruction in the interrupted microprogram is saved in a hardware interrupt return address register and the next microinstruction address is generated as a function of the particular hardware interrupt to be serviced. A microprogram dedicated to servicing the particular hardware interrupt is then entered at the hardware interrupt generated next microinstruction address. Logic is provided within each microinstruction to inhibit hardware interrupts.

Abstract: A data processing system executes a decimal multiply instruction by storing the product of a multiplier decimal digit and a multiplicand decimal digit in a read only memory and storing partial product decimal digits in a register. The units product decimal digit is read from the read only memory during one cycle and added to a partial product decimal digit. A resulting units carry is stored in a units carry flip-flop. The tens product decimal digit is read from the read only memory during another cycle and added to a higher order partial product decimal digit. A resulting tens carry is stored in a tens carry flip-flop. A multiplexer selects the output of the units carry flip-flop for adding the units carry during the next units cycle in which the next units product decimal digit is added to the higher order partial product decimal digit.

Abstract: A data processing system includes a central processing unit, a main memory, and a communication subsystem servicing a number of communication lines. The communication subsystem includes a free running timer, a line microprocessor for communicating with the communication lines and a shared memory, and an I/O microprocessor for communicating with the shared memory and the central processing unit and main memory. The line microprocessor, desiring to communicate with a specified communication line after a predetermined time delay, loads a first mailbox in shared memory with a binary number indicative of the predetermined time delay. The I/O microprocessor adds the output of the free running timer to the binary number, stores the result in a location in a random access memory, and periodically compares the result against the free running timer output. The I/O microprocessor loads a second mailbox with a control character when the results of the comparison indicate that the predetermined time delay is accomplished.

Abstract: Apparatus for testing dynamic noise immunity of digital integrated circuits wherein noise pulses of predetermined duration and amplitude are applied to the inputs of an integrated circuit under test. The tested circuit outputs which normally are at logic level 0 are connected to the inputs of a first group of control logic gates, while the tested circuit outputs which normally are at logic level 1 are connected to the inputs of a second group of control logic gates. The outputs of such groups feed a fault detection circuit. The input voltage thresholds of control logic gates is adjusted by suitable circuits so as to check the dynamic noise immunity of the integrated circuit under test for a predetermined logic swing.