Abstract: Apparatus for testing dynamic noise immunity of digital integrated circuits wherein noise pulses of predetermined duration and amplitude are applied to the inputs of an integrated circuit under test. The tested circuit outputs which normally are at logic level 0 are connected to the inputs of a first group of control logic gates, while the tested circuit outputs which normally are at logic level 1 are connected to the inputs of a second group of control logic gates. The outputs of such groups feed a fault detection circuit. The input voltage thresholds of control logic gates is adjusted by suitable circuits so as to check the dynamic noise immunity of the integrated circuit under test for a predetermined logic swing.

Abstract: A method for testing memory arrays embedded within electronic assemblies having other combinatorial logic elements connected to the inputs thereof. By following stated design rules, the embedded memory can be isolated from the combinatorial logic element and tested by use of a memory test subsystem either before or after the combinatorial logic elements are tested by a logic test subsystem. Both logic and memory tests are performed by a process that requires but a single handling of the electronic assemblies.

Abstract: Each electronically operated customer installable/replaceable unit module of a computer system is separately packaged to totally enclose the electronic/mechanical parts of each module within a box-like container or wrapper, the structure designed to maximize air flow through the system. This includes an electronics base module containing the basic logic circuits for the system, a power module containing all of the systems power supply circuits, and a pair of storage modules each containing the electronics and mechanical parts of a diskette device. The modules are loosely inserted into comparably shaped opened compartments of an enclosure base and bezel assembly constructed for toolless installation and removal of modules. An enclosure top cover which fits into the bezel contains finger-like protrusions in addition to embossing. When latched to the base and bezel assembly, the top cover correctly positions and holds the modules in place.

Abstract: A continuous form for a printer, suitable for office automation, consists of: (A) a plurality of contiguous sheets identified by reference marks regularly spaced along the form length having sheets of a first type with a preprinted heading being followed at a preestablished frequency in the form by sheets of a second type, without such preprinted heading, so that, when used in a printer provided with a cutter, by printing on selected sheets of the form and by cutting the printed sheets from the form and by collecting the printed sheets, letters, circulars and similar paper on several sheets of equal size and different type can be automatically obtained, or (B) in an alternative embodiment, a plurality of identical contiguous sheets each comprising a preprinted head zone and a tail zone, both zones having the same height, the length of the sheets exceeding a desired final sheet length by the height of the tail zone, so that letters, circulars and similar papers on several sheets of equal size and different typ

Abstract: A document holder attachable to a display terminal used to support one or more documents to be referenced by the display terminal user when information is entered or displayed on the display terminal screen is disclosed. The document holder is supported by an easel bracket which fits in an annular groove in the display terminal cover. The document easel is attached to the easel bracket such that an adjustment in the swivel or tilt of the display terminal for operator viewing convenience also results in a corresponding adjustment in the document holder such that the document holder always remains in the same relative viewing position with respect to the display terminal screen. The document holder can be easily added or removed from the display terminal and is reversible for either righthanded or lefthanded use.

Abstract: An interactive terminal data processing system includes a number of work stations, all coupled in common to a single conductor coaxial bus which may be up to one kilometer in length. Work stations may be connected to the bus by up to a ten foot coaxial cable with the connection to the bus being typically no less than thirty feet apart.

Abstract: An address bus of a central processor unit (CPU) is tested by generating repetitive "no operation" (NO OP) instructions. A microprocessor in the CPU receives the NO OP instruction code set manually into switches and generates sequential addresses on successive CPU cycles on the address bus. The microprocessor generates a read signal during each CPU cycle which is jumpered to portions of the logic to allow continuity of operation during test.

Abstract: A decoding logic system in a logic control system of a data processing system is disclosed, wherein the data processing system is comprized of a main memory unit communicating with the logic control system by way of a common communication bus, and wherein the logic control system and a CPU (central processing unit) communicate by way of a local communication bus. In response to a CPU request, CPU instructions stored in the main memory unit are received by the logic decoding system, and presented to the CPU in such a manner as to accommodate both memory bit and CPU computed bit modifications to the instructions during instruction execution, while avoiding interruptions in CPU activity caused by information transfer delays internal to the logic decoding system. Instruction modification also may be effected by incrementing or decrementing the instructions under firmware control.

Abstract: A data processing system includes a main memory system which couples in common with a central processing unit to a bus for transfer of data between the central processing unit and memory system. The memory system includes a plurality of memory controllers, each of which controls the operation of a number of memory modules. Each controller also includes reconfiguration apparatus for enabling reconfiguration of the memory system upon detection of a fault. The reconfiguration apparatus includes apparatus for identifying the type and design revision of the controller associated therewith enabling more expeditious fault diagnosis based upon status signals provided by the controller during diagnostic testing by the central processing unit.

Abstract: A logic control system is disclosed for accommodating the flow of both procedural information and CPU (central processing unit) instructions from a central memory system to a CPU without compromising memory bandwidths or CPU execution speeds because of transfer delays or timing variances. Instruction modifications and plural task assignments are accommodated during instruction execution.

Abstract: A logic control system is disclosed for accommodating the flow of both procedural information and CPU (central processing unit) instructions from a central memory system to a CPU without compromising memory bandwidths or CPU execution speeds because of transfer delays or timing variances. Instruction modifications and plural task assignments are accommodated during instruction execution.

Abstract: The directory and cache store of a multilevel set associative cache system are organized in levels of memory locations. Round robin replacement apparatus is used to identify in which one of the multilevels information is to be replaced. The directory includes parity detection apparatus for detecting errors in the addresses being written in the directory during a cache memory cycle of operation. Control apparatus combines such parity errors with signals indicative of directory hits to produce invalid hit detection signals. The control apparatus in response to the occurrence of a first invalid hit detection signal conditions the round robin apparatus as well as other portions of the cache system to limit cache operation to those sections whose levels are error free thereby gracefully degrading cache operation.

Abstract: A logical control system is provided for accommodating both single and double byte accesses to a video terminal system display memory to supply video character and visual attribute data to a video screen without limiting the quantity of visual attributes and without the needless occupation of video screen character positions by visual attribute characters.

Abstract: A microprogrammed commercial instruction processor (CIP) is placed in a stall mode during the transfer of information between the CIP and main memory by stalling a free running clock signal. When the transfer of information is completed, the free running clock cycles. If main memory indicates an error condition, then the free running clock signal is again stalled after one cycle to allow the firmware in the CIP to process the error.

Abstract: A switching regulator power supply operates at a variable high frequency with low power dissipation and a minimum of complexity. The transformer primary windings are included as part of a self-starting circuit which starts a pulse generator having a fixed frequency and variable pulse width. The self-starting circuit includes a control circuit network which connects to the transformer primary windings and a low voltage regulator circuit connects to the pulse generator and network. The control circuit network provides the voltage regulator circuit with the desired current characteristics of high instantaneous current during a short turn-on time interval and a zero current during power supply operation. The self-starting circuit in response to the input rectified AC power after the short turn-on period of time applies sufficient voltage which enables the pulse generator to begin generating a first output pulse.

Abstract: A logic control system comprised of a cache memory system and a transfer control logic unit is disclosed for accommodating the flow of both procedural information and CPU (central processing unit) instructions from a central memory system on a common communication bus to a CPU. The CPU and the transfer control logic unit communicate by way of the cache memory system with the common communication bus. In response to a CPU request to the central memory system, procedural information and instructions are requested by the transfer control logic unit from the cache memory system and presented to the CPU in such a manner as to avoid interruptions in CPU activity caused by information transfer delays.

Abstract: One or more common buses are provided for coupling a plurality of units in a data processing system for transfer of information therebetween. The central processing unit (CPU) allocates the one or more common buses to one of the requesting units as a function of request type and on which of one or more common buses the requesting unit is located. Bus requests are generated in a synchronous manner by use of a timing signal originating in the CPU which is connected in series between the one or more units on each of the one or more common buses.

Abstract: A hardware monitor interface unit (HMIU) is coupled to a data processing system. Programmable hit matrices (PHM's) in the HMIU store information which is compared with information from the data processing system. The PHM's generate "hit" signals indicating comparison. These "hit" signals are received by monitors coupled to the HMIU which are used to compile the data processing system performance data. Appartus in the HMIU generates clocking signals enabling the information to be received by the HMIU and generates strobing signals to be used for timing the "hit" signals and other control signals received by the monitors.

Abstract: A switching regulator power supply operates at a variable high frequency and pulse width with low power dissipation and a minimum of complexity. The transformer primary windings which are included as part of a self starting circuit start a pulse generator having a variable pulse width and variable frequency. During operation, the input RC network of the pulse generator, in response to the input rectified AC line voltage, conditions the pulse generator to generate output pulses whose widths vary as a function of changes in the input rectified AC voltge. An error circuit coupled to the secondary winding compares the output DC supply voltage to a reference voltage and generates an error signal which is applied through a coupling circuit for further adjusting the frequency of the pulse generator within a desired range to existing load conditions.

Abstract: A stepping motor drive circuit having pairs of magnetically coupled phase windings (1, 3 and 2, 4), comprises current chopping control circuits (23, 24) for controlling the on/off switching of a plurality of driving transistors (5, 6, 7, 8) each coupled to a respective phase winding, and the circuits associated with each switching transistor for reducing their storage times and hence switching losses. More particularly, with reference to the switching transistor (5), the related circuit for storage time reduction comprises a series connected capacitor (25) and a diode (45). The circuit connects between one terminal of one winding (2) of the pair of phase windings which is magnetically coupled to the one winding (1) of the other pair connected to such switching transistor (5) and to the base of such transistor (5). As soon as the transistor (5) is caused to switch from ON to OFF, the circuit applies a reverse voltage pulse to the base of the transistor (5) causing a fast transition towards the cutoff region.