Abstract: Accurate detection of an existing link (current road location between two road nodes) of a vehicle by an on-board navigation system. Upon each periodic detection of the position, azimuth and velocity of the vehicle by a GPS receiver, all the links within a predetermined distance of the vehicle position are extracted by looking up road data read out from a CD-ROM. For each of the links, the distance from the vehicle position, the angle with the vehicle azimuth, the angle between the vehicle azimuth and a passable direction of the link, the difference between the vehicle velocity and the speed limit for the link and the connectability with the last-detected existing link are obtained and are substituted into a predetermined existential probability evaluation function to calculate an existential probability. The link with the largest existential probability is determined to be the existing link.

Abstract: In an electronic device in which a control unit is detachable from an equipment body, the control unit is engaged and detachably secured to the equipment body by a locking member and a temporary retaining member. A lock release unit causes the locking member to disengage the control unit. When the locking member disengages the control unit, the temporary retaining member retains the control unit and causes the control unit to protrude from the front of the equipment body. Thus, the control unit is temporarily retained by the temporary retaining member in the protruding position and is not allowed to fall off the equipment body onto the ground or floor. In addition, since the operating member is moved to a position where it protrudes from the front of the equipment body, the control unit is easy to remove by hand.

Abstract: A structure and method of performing an analog-to-digital conversion uses a voltage generator which generates an analog reference signal in response to a clock signal. The analog reference signal is a ramp signal which varies between two on-chip supply voltages. A voltage divider circuit receives an analog input signal to be digitized and the analog reference signal. The voltage divider circuit creates an analog control signal equal to the sum of a predetermined fraction of the analog input signal and a predetermined fraction of the analog reference signal. The analog control signal is provided to a first digital buffer and the analog reference signal is provided to a second digital buffer. The first and second digital buffers provide digital control signals having a first logic state when the applied input signal is less than a threshold voltage and having a second logic state when the applied input signal is greater than the threshold voltage.

Abstract: An integrated circuit one shot circuit provides relatively long duration (hundreds of nanoseconds up to a millisecond) output pulses without the need for excessively large transistors. The one shot circuit includes a pull up and a pull down device connected to the one shot circuit's input terminal, with a latch connected to a node between the pull up and pull down devices. The output terminal of the latch is connected to the input of a Schmitt trigger. One terminal of a grounded capacitor is connected between the latch output terminal and the Schmitt trigger input. The output terminal of the Schmitt trigger is connected through an inverter to one input terminal of a NAND gate, the other input terminal of which is connected to the one shot circuit's input terminal. A feedback line connects the output terminal of the NAND gate to the gate of a depletion mode transistor which is between the pull up and pull down devices.

Abstract: An improved Schmitt trigger, especially useful for large scale integrated circuit applications, includes a buffer (inverter) having a pull up device and two pull down devices all connected between a voltage supply and ground, and each receiving the input signal at its gate terminal. A node between the output terminals of the pull down devices is connected to the output terminal of the Schmitt trigger. A feedback line connects the output terminal of the Schmitt trigger to the gate of an N-channel depletion device connected between the pull-up and pull-down devices. Also provided are two devices to control the timing of the Schmitt trigger; these two control devices are connected between the output terminal of the Schmitt trigger and the output terminal of the inverter.Also provided in one embodiment is electrostatic discharge protection connected to the Schmitt trigger input and output terminals, and in another embodiment a control device for turning on and off the supply voltage to the inverter.

Abstract: A CMOS or NMOS output buffer equalizes the number of logic gates in the signal paths connected to both the pull up and pull down transistors. In one embodiment, the pull down transistor signal path includes the conventional inverter connected to the output of a NAND gate. The pull up transistor signal path includes a CMOS passgate including two transistors connected together controlled by the output enable signal and passing the output data signal to a conventional output inverter stage. Also an additional transistor controlled by the output enable signal provides an additional signal to the input of the pull up transistor output inverter stage when the output enable signal is low. The provision of balanced signal paths in terms of number of gates and therefore propagation time to both the pull up and pull down transistors evens out the rise and fall crowbar switching current and thus minimizes switching noise.

Abstract: Highly integrated programmable arrays, in which a logic array integrated circuit chip is divided into configurable logic blocks interconnected by configurable interconnect lines, have been programmed by automatic means and methods. The present invention provides for allowing a user to manually specify the partitioning of a logic design, and to allow a user to retain portions of a previously partitioned, placed, and routed design when making revisions. To allow for manual control of partitioning, a library of symbols includes a partitioning symbol that specifies which primitive logic functions can be grouped. The user specifies which ports of primitive logic functions will correspond with ports on the logic block symbol. The present invention also allows for partitioning parts of a design before combining the parts.

Abstract: A control circuit for a multi-stage power amplifier (such as in a portable radio transmitter) compensates for fluctuations in ambient temperature, load, signal level and power supply voltage, The control voltage is set by comparing a biasing level which is related to the amplifier input signal level to a voltage proportional to the power supply current of the last stage of the amplifier. The control voltage resulting from the comparison establishes the operating point of the last stage of the power amplifier.

Abstract: An automatic volume control to prevent the listener from having an odd sensation is obtained with a plurality of conditions taken into considerations. A plurality of control rules required to infer using fuzzy logic a volume correcting value on the basis of frequency band component levels, L, M and H and a volume level V are stored beforehand in a volume correcting value inferring portion 13. The volume correcting value inferring portion 13 obtains inference results of the individual control rules on the basis of the individual frequency band component levels L, M, H input from a filter circuit 12 and the volume level input from an audio reproducing portion 14, obtains a weighted mean of the respective inference results as a volume correcting value Z, and inputs the volume correcting value to the audio reproducing portion 14 to automatically correct the volume.

Abstract: A computer aided design system for electronic digital circuitry allows the circuit designer to design a circuit using high level block components, The designer specifies data type and precision (bus width) parameters as desired for whichever circuit blocks and/or busses he desires, Then the system propagates the data types and precision throughout the design automatically to achieve circuit-wide consistency, The system can also be used to verify a circuit design for data type and bus width consistency, The system can also be used to determine the mode of operation for the circuit blocks in the circuit.

Abstract: A method and apparatus for reliably determining an optimal route between a departure point and a destination in an exploration object zone, the optimal route being determined according to the situation of roads separating the departure point and the destination. Prior to route exploration, an area determiner counts the total number of intersection network lists associated with a route exploration object zone, which lists are stored in a route exploration memory. When a density of intersections (which is the total number of intersection network lists divided by the size of the route exploration object zone) exceeds a certain value, the area determiner determines that the object zone lies in an urban (high road density) district. When the density of intersections is smaller, the area determiner determines that the object zone lies in a suburban (low road density) district.

Abstract: A disk reproducing apparatus enables selection and reproduction of the desired programs recorded on a disk, with reduced memory capacity. When a desired program is selected using the operating panel, a system controller moves an optical pickup to the TOC area of the read-in region of a read-only mini-disk, causes the optical pickup, RF amplifier and digital signal processing circuit to read the start address of the desired program from the TOC area, thereafter again moves the optical pickup while observing the address data in the subdata input from the digital signal processing circuit, then searches the heading position of the desired program on the disk and starts reproduction of the desired program, upon completion of the searching operation.

Abstract: A hybrid EPLD (chip) architecture has multiple first blocks each including a first type programmable AND array and multiple first type macrocells which are complex in structure and highly configurable; and multiple blocks each including a second type programmable AND array having fewer input lines and product term output lines than does the first type AND array, and multiple second type macrocells which have fewer logic gates than do the first type macrocells. The EPLD has a programmable interconnect matrix for interconnecting all the blocks.

Abstract: The bit line for reading data in or writing data out from a CMOS integrated circuit latch is precharged to the trip point voltage of the latch (as determined by the latch's transistor design) shortly before the occurrence of a read operation. The precharging circuitry uses the latch circuit itself to generate the trip point, hence ensuring that the precharging circuit operates properly with regards to the latch characteristics in spite of temperature, voltage and fabrication process variations. The precharging circuitry ensures that during the operation of reading data from the latch, the bit line voltage never causes the latch to completely switch states, since at most the bit line voltage asymptotically approaches the trip point voltage. The precharging circuit is relatively simple, including only two logic gates and three other transistors.

Abstract: A programmable logic device having macrocells enables gate cascades between macrocells to occur with a faster signal transit time, while preserving the flip flop function of the cascaded macrocells by reallocating a redirectable flip flop reset product term to the flip flop input. All gate product terms are retained during cascading. The macrocell logic is optimized for fast signal transit with selectable flip flop clocking. Multiplex clocking and programming are done with fewer transistors in the signal path, further reducing signal transit time.

Abstract: More than one security bit is used in a block of a PLD chip. The internal configuration and other information is left unprotected when all the security bits are in the erased state, and is protected by programming one or all the security bits. The security bits are located physically in proximity to the areas containing configuration and any other user-defined data, both so that they are difficult to discover and so that the erasure of all security bits in a EPROM-based PLD would cause a large number of adjacent user-defined bits to be erased as well, hence making it very difficult to extract useful information from a protected device by reverse engineering. Situating security bits in a different, pseudorandom location within each block of the chip makes them difficult to find and so further inhibits reverse engineering.

Abstract: An amplifier for a radio transceiver overcomes the problem of gain being dependent on ambient temperature. Transmission power is matched to strength of a received signal by providing matched dual gate FET amplifier stages in both the transmitter and receiver portions of the transceiver. Changes in gain due to temperature are compensated for by detecting changes in the FET drain current by measuring the source voltage of the amplifier. The FET source voltage is compared to a reference voltage, and the output signal resulting from the comparison is provided as a control signal to one of the FET gates.

Abstract: A car security system has a proximity sensor such as a radar sensor with variable sensitivity and capable of producing a detection signal upon detecting motion of a person in a monitoring area. A control circuit is provided controls the sensitivity of said proximity sensor. The system also has a monitoring/alarming control circuit for control of predetermined monitoring and alarming control on the basis of the output from the proximity sensor, and alarming devices such as a headlight flash circuit, buzzer and siren for performing a predetermined alarming operation under the control of the monitoring/alarming control circuit. The sensitivity control circuit operates in response to a predetermined operation such as an arming start operation to vary the sensitivity of the proximity sensor so as to automatically set the sensitivity to a first sensitivity level which is the highest level within a range which does not cause the sensor to produce the detection output.

Abstract: A programmable circuit is provided with a number of current regulating circuits, such as sense amplifiers, by which the user can regulate the amount of current drawn by any of a number of circuit functions within the programmable circuit. Additional current regulating circuits are associated with circuit elements which can be programmably shared between one or more circuit functions. The user can therefore programmably control the current consumption, and thereby the speed, of each circuit function as well as circuit functions interacting via the shared circuit elements.

Abstract: A feedback circuit for input pads of an integrated circuit where one or more of the input pads may not be bonded to a package pin when the pad is packaged or alternatively is bonded but the pin is not externally connected. The feedback circuit includes a transistor connected between the input pad and the output of the first associated input buffer so that whenever the integrated circuit is at a steady state, i.e. is off or has been powered on, no direct current is drawn by the pad because the unbonded pad is forced to be either in the high or low state by the feedback transistor. The feedback transistor may be a pull down device or a pull up device or a full inverting gate; in any case the feedback device draws no direct current when the input pad connected thereto is at its fully high or fully low state voltage.