Abstract: The present invention teaches a method and structure of enhancing the current gain characteristics of a bipolar junction transistor using a semiconductor substrate comprising a base, an emitter and a collector and an interface at the emitter, such that a carrier current conducts between the base and the emitter. Further, a first polysilicon layer is formed superjacent the interface, and is implanted with O.sub.2. Subsequently, the substrate is heated such that the emitter interface is obstructed by a silicon dioxide formation, thereby blocking a portion of carrier current from passing through the interface.

Abstract: The present invention teaches a system for measuring the height of an object having an outer surface. The system comprises a system for generating an energy beam along a path, such as light, having a structured pattern, wherein the structured pattern of the energy beam irradiates the outer surface of the object. The structured light pattern comprises a constant dimension. The system further comprises a sensor for sensing the outer surface of the object irradiated by the structured pattern. Moreover, the system comprises a system for calculating the height of the object in response to the constant dimension of the structured pattern irradiating the outer surface of the object and sensed by the sensor. This system for calculating the height of the object preferably comprises a programmed computer containing a series of algorithmic steps for deriving a refined overall height profile of the object.

Abstract: The present invention teaches an integrated circuit ("IC") gate array having improved reliability and increased immunity to deep space interference from electromagnetic radiation, photon energy, and charged particles. In one embodiment of the present invention, the gate array comprises a first and a second logical component, and a first and a second isolation transistor. Both first and second isolation transistors comprise an input, a biasing bus having a voltage potential, and an electrical contact for electrically coupling the biasing bus with the input. Moreover, the gate array comprises a redundant coupling for increasing the immunity of the gate array to charged particles, electromagnetic radiation and photon energy.

Abstract: The present invention teaches a low voltage coefficient MOS capacitor, and a method of making such a capacitor, having substantially uniform parasitic effects over an operating voltage range and a low voltage coefficient. The capacitor comprises a first conductive layer superjacent a silicon on insulator ("SOI") substrate. The first conductive layer comprises heavily doped silicon having a first conductivity type, while the substrate comprises a second conductivity type. Further, the capacitor comprises an isolation trench surrounding the first conductive layer filled with a dielectric material. Positioned superjacent the first conductive layer is a dielectric layer, thereby forming a dielectric shell on all sides of the first conductive layer except for its upper face. Moreover, a second conductive layer is positioned superjacent the dielectric layer to form a low voltage coefficient capacitor.

Abstract: A multi-port memory device includes a row-column array, a random access port, a plurality of bidirectional serial access memory (SAM) ports, and a switching network. There is one SAM port for each of a plurality of sets of columns. The switching network selectively couples each SAM port with each set, each set with each other set, and each SAM port with each other SAM port. A video random access memory (VRAM) or a multi-port dynamic random access memory (DRAM) of the present invention provides increased flexibility in smaller die area.

Abstract: The present invention teaches a touch activated switch. The switch comprises a light source for generating a light ray. Further, the switch comprises a first lens for collimating the light source's light ray. The first lens, as a result, generates a collimated light ray in a first direction. In a second direction, the first lens forms a first and a second focal point, such that the light source is positioned at the first focal point. Moreover, the switch comprises a second lens for converging the collimated light ray to a surface. This surface scatters the collimated light ray in the direction of the first lens when the surface is substantially touched. The switch also comprises a detector for detecting the collimated light ray which have been scattered by touching the surface, with the detector being positioned at the second focal point, such that the switch is activated in response to touching the surface.

Abstract: The present invention teaches a method and structure of enhancing the current gain characteristics of a bipolar junction transistor. The method comprises the step of forming a patterned silicon dioxide layer superjacent a semiconductor substrate comprising a base, an emitter and a collector, such that a carrier current conducts between the base and the emitter. The silicon dioxide layer forms an interface on the substrate at the emitter. Further, a first polysilicon layer is formed superjacent both the patterned silicon dioxide layer and the interface, and is implanted with O.sub.2. Subsequently, the substrate is heated such that the emitter interface is obstructed by a silicon dioxide formation, thereby blocking a portion of carrier current from passing through the interface.

Abstract: A Field Emission Display ("FED") is disclosed having an array of display grids formed within a region of a semiconductor substrate. The array is defined by a number of rows and a number of columns. Further, a multiplicity of field emitter tips are incorporated for driving the array, each of the tips being coupled with a display grid of the array. To select any row of the array, a row select switch is employed. The row select switch is preferably formed outside the region of the substrate. In operation, a row is selected when a row control signal is received by the row select switch. Further, a column select switch for selecting any of said columns is also employed, formed outside the region. In operation, a column is selected when a column control signal is received by the column select switch. Moreover, a plurality of constant current sources, formed outside the region, are provided for generating a constant current to each of the tips.

Abstract: A method for fabricating semiconductors is provided in which a conformal layer is formed superjacent at least two conductive layers. The conformal layer has a thickness of at least 50 .ANG.. A barrier layer is then formed superjacent the conformal layer to prevent subsequent layers from diffusing into active regions. The barrier layer is preferably Si.sub.3 N.sub.4. A glass layer is then formed superjacent the barrier layer. The glass layer has a thickness of at least 1 k.ANG.. The glass layer is heated to a temperature of at least 800.degree. C. for at least 15 minutes while introducing H.sub.2 and O.sub.2 at a high temperature to cause vaporization, thereby causing the glass layer to reflow. Next, the glass layer is exposed to a gas and radiant energy for 5 to 60 seconds, thereby making said glass layer planar. The radiant energy generates a temperature within the range of 700.degree. C. to 1250.degree. C. Further, the gas is at least one of N.sub.2, NH.sub.3, O.sub.2, N.sub.2 O, Ar, Ar-H.sub.2, H.sub.

Abstract: The present invention teaches a memory comprising an array of memory cells. Each cell of the array in the memory comprises a bus, and a diode, preferably a zener diode, having a substantially low breakdown voltage. Further, each cell comprises a programmable element, preferably an antifuse, for selectively coupling the diode with the bus.

Abstract: The present invention teaches a method and system for disconnecting shorted decoupling capacitors, wherein a semiconductor chip having a plurality of redundant decoupling capacitors. Each of the capacitors is coupled, by means of a link, to a bus having a predetermined voltage. Each link is accessible to light emissions, in planar view. The system comprises a tester for testing the operability of each of the capacitors. In a preferred embodiment, the tester comprises a heating element and a high voltage stress testing element. Under thermal and voltage stress, an infrared signal identifying shorted decoupling capacitors is generated by shorted decoupling capacitors. The system further comprises a sensor for sensing the infrared signal. In one embodiment of the present invention, the sensor comprises an emission microscope for multilevel inspection ("EMMI"). Each inoperable capacitor is decoupled from the bus by disintegrating the link with a laser in response to the infrared signal.

Abstract: A method and system for fabricating semiconductor wafers is disclosed, wherein a rugged and/or smooth, atomically clean, semiconductor substrate is provided in a rapid thermal processing ("RTP") chamber. The substrate can be single crystal, polycrystalline or amorphous silicon. In one embodiment of the present invention, the substrate is cleaned by exposing it to at least one of CF.sub.4, C.sub.2 F.sub.2, C.sub.2 F.sub.6, C.sub.4 F.sub.8, CHF.sub.3, HF, NF.sub.6, and NF.sub.3 diluted with Ar-H.sub.2 at a temperature substantially within the range of 650.degree. C. to 1150.degree. C. for approximately 10 to 60 seconds in the chamber. Subsequently, the clean substrate is exposed to a first gas and energy generating a first temperature substantially within the range of 650.degree. C. to 1150.degree. C. in situ under substantially high vacuum for approximately 5 seconds to 20 seconds. Simultaneous to exposing the substrate to the first gas, a second gas comprising fluorine as an oxidizing agent, preferably NF.