Abstract: A double-sized chip assembly and method is provided for two back-to-back integrated-circuit chips which both have the same fabrication mask sets. An electrically-selectable bonding-pad connection option alternatively provides a standard, non-reversed, option NRO for a bonding-pad layout and a non-standard, reversed option RO for the layout of the bonding-pads. The double-sized, back-to-back, wire-bonded integrated-circuit chip assembly and method includes a pair of integrated-circuit chips, each having one or more reversible wire-bonding-pads. One of the chips has its wire-bonding-pads electrically reversed such that the wire-bonding pads on both chips are located near each other to accommodate wire-bonding to a common bonding finger of a lead frame. A bonding-option wire-bonding-pad has an external voltage applied to it to indicate whether the integrated-circuit chip is to provide a standard pattern for the reversible wire-bonding-pads, or a reversed pattern for the reversible wire-bonding-pads.

Abstract: A laser precision bore sight assembly and method aligns a laser beam along the longitudinal axis of a gun barrel. At the proximate end of an elongated bore shaft is rotatably mounted a compressible barrel insert with a continuous outer surface which resiliently engages the inside wall of the gun barrel to coaxially align the longitudinal axis of the proximate end of the shaft with the longitudinal axis of the gun barrel. The exterior surface of an alignment cone is provided on the distal end of the bore shaft. A battery/switch housing, containing a switch assembly, cooperates with a laser housing assembly to provide an enclosure for a battery. A laser source in the laser housing assembly provides a laser beam in a direction coaxial with the longitudinal axis of the shaft. Matching threads provide for relative longitudinal movement such that a terminal of the battery engages the switch assembly to activate the laser source.

Abstract: A method and apparatus for simultaneously communicating a first data stream along with a second data stream. A first carrier is modulated with a first data stream and a feature of the modulated first carrier is then imposed under the control of a second independent data stream. The modulated first carrier with the imposed feature is then demodulated to provide the first data stream. The distinguishable feature of the modulated first carrier is then detected to provide the second data stream. The first and the second data streams are clocked at rates which are integer multiples of each other. The distinguishable feature of the modulated first carrier includes the amplitude of the modulated first carrier or the frequency of the modulated first carrier. M-ary information is transmitted by transmitting groups of 3 or more bits simultaneously by using distinguishable amplitude or frequency values of a feature imposed on a first carrier.

Abstract: One or more reinforcement pins are inserted between the lid and base of a sealed integrated-circuit package. The reinforcement pins reinforce a sealing layer between the lid and the base, particularly against shear forces exerted on the sealing layer between the lid and the base of a package. Shorter pins are provided which do not extend through the lid or base. Longer pins are provided which extend through the lid or base, with the ends of the pins being mechanically secured to the lid or base and sealed with solder, glass, or epoxy material.

Abstract: An incoming memory address signal is compared and matched with static signals provided by a fuse array that represents an address of a defective memory column that is being replaced by a redundant memory column in a memory chip. Each section of a memory is provided with a redundant memory column. Each redundant column of the memory is connected to a separate redundant-column sense amp that is activated by a memory section-select signal in combination with a BIGHIT signal. The BIGHIT signal indicates that the memory chip has received an address of a defective memory column. All of the output terminals of the redundant column senseamps are connected in common to a redundant internal data bus RDINTDB. A defective-column-address detector circuit compares an incoming multi-bit memory address signal to an address of a defective memory column and provides an address-hit signal ADDHIT if a match occurs therebetween.

Abstract: A method and apparatus for simultaneously communicating a first data stream along with a second data stream. A first carrier is modulated with a first data stream and a feature of the modulated first carrier is then imposed under the control of a second independent data stream. The modulated first carrier with the imposed feature is then demodulated to provide the first data stream. The distinguishable feature of the modulated first carrier is then detected to provide the second data stream. The first and the second data streams are clocked at rates which are integer multiples of each other. The distinguishable feature of the modulated first carrier includes the amplitude of the modulated first carrier or the frequency of the modulated first carrier. M-ary information is transmitted by transmitting groups of 3 or more bits simultaneously by using distinguishable amplitude, frequency or time of occurrence values of a feature imposed on a first carrier.

Abstract: A high density leaded ball-grid array package for packaging an integrated-circuit die includes a laminated substrate formed of a non-conductive layer sandwiched between first and second conductive trace patterns. A leadframe is directly attached onto the first conductive trace pattern of the laminated substrate by a non-conductive adhesive so that the open portion thereof overlies a central region of the laminated substrate. An integrated-circuit die is mounted in the central region of the laminated substrate. Bonding wires are interconnected between bonding pads formed on the integrated-circuit die and bonding fingers formed on the leadframe. A plastic material is molded over the top surface of the die, bonding fingers and bonding wires. A solder mask is applied on the second conductive trace pattern so as to form selective solderable areas. Finally, solder balls are attached to the selective solderable areas.

Abstract: Thin organic layers are laminated on both the top and bottom of a relatively thin ceramic layer to form a reliable thinner composite substrate for packaging a chip-scale flip-chip die in a thin package. A semiconductor die has a number of solder bump-mounting pads formed thereupon which are connected with solder bumps to mounting pads on the top surface of the thin composite substrate.

Abstract: An improved adaptive equalizer providing the proper amount of equalization to restore the missing frequency components of a received and underequalized waveform. The invention'equalization gain or pulse counting feature can be set at various levels by digitally programming the control logic of the invention. Additionally, the digital control features of the invention permit higher accuracy in determining required equalizations for waveforms and avoid variations, such as temperature process variations, present in analog systems. The invention permits higher accuracy in determining required equalizations for waveforms. The invention finds, holds, and updates the average low frequency peak of the incoming signal in a highly digital manner. Since peak information is digitally held, it is not subject to the data dependent drifts inherent in analog peak detectors.

Abstract: A voltage detector circuit discriminates between a 13 volt Programming signal and a 6 volt signal without creating a field across the gate oxide of a sensing transistor in excess of 7.0 MegaV/cm. A PMOS transistor has a source terminal and a substrate terminal connected, both connected to the input terminal, A gate terminal is connected to a VCC voltage level. A shunt NMOS transistor has a drain terminal connected to the drain terminal of the PMOS transistor and a source terminal connected to a ground terminal. A gate terminal of the shunt NMOS transistor is connected to the VCC voltage level. The NMOS transistor is turned on to provide a shunt resistance between the drain terminal of the PMOS transistor and ground. A drain terminal of a series NMOS transistor is connected to the drain terminal of the PMOS transistor. A gate terminal of the series NMOS transistor is connected to VCC. The source terminal of the series NMOS transistor is connected to a sensing output terminal.

Abstract: A semiconductor integrated circuit package is provided with insulated bonding wires. The semiconductor die is mounted to a base of either a leadframe or a grid-array package. A plurality of bonding wires are bonded between bonding pads on the semiconductor die and bonding fingers at inner ends of package conductors. The bonding wires have a PECVD SiO2 layer formed thereupon to thereby provide electrically-insulated bonding wires to prevent short-circuits between adjacent bonding wires. After wire bonding of the bonding wires, an insulating PECVD SiO2 layer is formed on the bonding wires to prevent short-circuits with adjacent wires. An SiO2 layer is simultaneously formed on a leadframe and is removed from the outer ends of the leads by blasting with a medium.

Abstract: A memory-test-mode detection circuit for an integrated circuit uses one or more of the input pins of an integrated circuit to detect at least one non-standard signal level. To avoid false triggering several other non-standard logic levels can also be used with some of the other input pins. Each of the non-standard signal levels are detected by a separate signal level detection circuit. A predetermined combination of input signals then provides a control signal which sets the integrated-circuit into a predetermined test mode. A non-standard Vcc/2 signal level is detected by determining that it is above a predetermined low threshold level of 1/4 Vcc and below a predetermined high threshold level of 3/4 Vcc. Additional non-standard input signal levels which are close to Vcc and Vss are also used. A chip enable (CEX) signal is used to enable the signal level detection circuit when a chip is enabled.

Abstract: A current-controlled oscillator (ICO) circuit including an all p-channel transistor based ring oscillator, a first current mirroring stage, and a second current mirroring stage. The all p-channel transistor based ring oscillator, p-channel transistors in the input structure of each amplification stage, and metal lines in the ring and from the ring to the amplification stages over an n-well improve noise immunity and tolerance. The first current mirroring stage utilizes an input current to generate a first voltage controlling a series of differential delay cells connected in a ring topology that forms the ring oscillator. The second mirroring stage utilizes a precision current to generate a second voltage controlling at least one amplification stage, which converts corresponding delay cell output signals to a single-ended logic level signal compatible with external circuitry needs.

Abstract: A technique for demodulating a message signal from an angle modulated carrier signal. A noncoherent, independent, periodic reference is generated to have a predetermined phase characteristic and which is noncoherent with and independent of the angle modulated carrier signal. The phase of the reference is then compared with the phase of the carrier to determine the message signal on the angle modulated carrier. The phase of the noncoherent, independent, periodic reference is associated with a measured value for the reference. The phase of the angle modulated carrier signal is associated with a voltage value for the angle modulated carrier signal. These values are measured and then compared to determine the message signal on the modulated carrier signal. Time variations of the comparison of values are directly related to the message signal in the case of a PM carrier. Changes in the time variations of the voltage comparison are related to the message signal for a FM carrier.

Abstract: An improved invention providing a solution to a problem endemic to conventional adaptive equalizer systems, a problem known as baseline wander. The invention brings the baseline back down when it has drifted up due to baseline wander. The invention brings the baseline back up when it has drifted down due to baseline wander. The end result is that the invention keeps the data centered about the common mode, thus helping to ensure that the data is equalized properly without distortion.

Abstract: A trip meter, such as a taximeter or a mileage meter for a commercial vehicle, such as a truck, are combined with an integral GPS receiver/computer which provides GPS position and time information. Odometer input pulses to the trip meter are accurately calibrated by using GPS position, velocity, and time information to generate corrected odometer pulses which are provided to the odometer input terminal of the trip meter. The GPS system is integrated into the trip meter for calibrating and cross checking of the input odometer pulses to provide reliable, consistent distance measurements by the trip meter. GPS position, velocity, and time information produce incontrovertibly accurate corrected, odometer input pulses and GPS time signals for the trip meter to precisely compute elapsed time and distance traveled. A backup dead-reckoning subsystem operates when the GPS receiver has service outages.

Abstract: A ball grid array (BGA) package configuration for packaging an integrated-circuit die includes a lead frame having a plurality of inwardly-extending bonding fingers and a centrally-located die-attach pad. The bonding fingers are disposed peripherally surrounding the die-attach pad. An integrated-circuit die is mounted on the die-attach pad. Bonding fingers are interconnected between the bonding pads on the integrated-circuit die and the plurality of bonding fingers. A plastic material is molded over the top of the lead frame and the die while still providing an exposed bottom surface of the bonding fingers on the lead frame. A solder mask is disposed over the bottom of the lead frame so as to form selective solder areas. Solder balls are attached to the selective solder areas.

Abstract: A die-up configuration includes a rigid circuit board with electrically conductive plated-through holes formed therethrough and an integrated-circuit die mounted to the upper surface of which a flexible insulated tape layer is fixed to the upper surface of a rigid circuit board and which has a number of wire-bonding sites. Conductive vias or plated-through holes are provided for connecting the wire-bonding sites on the upper surface of the flexible insulated tape layer to the contact areas formed on the lower surface of the flexible insulated tape layer. Conductors are provided for connecting respective contact areas on the lower surface of the flexible insulated tape layer to solder balls on the bottom of the rigid circuit board.

Abstract: A method and apparatus for a reinforced leadframe to substrate attachment in a semiconductor assembly. In one embodiment, a printed circuit board having a plurality of electrically coupled electrical contact regions and wire bond areas formed thereon has a leadframe attached thereto such that each of the bonding fingers of the leadframe is coupled to a respective electrical contact region on the printed circuit board. A ribbon of B-staged epoxy is disposed on the leadframe such that said leadframe is disposed between the ribbon of B-staged epoxy and the printed circuit board. An integrated-circuit die is mounted on the printed circuit board with the bonding fingers of the leadframe peripherally surrounding the integrated circuit die. The bonding pads on the integrated-circuit die are electrically coupled to respective wire bond areas on the printed circuit board.