Abstract: A mounting system attaches directly to a square or round trigger guard of a firearm. A separate trigger guard mount assembly includes a base having a groove formed therein for receiving a forward portion of a trigger guard of the firearm. A trigger guard mount clamp for attaches the trigger guard mount base to the forward portion of a trigger guard. A screw-operated clamp removably attaches a light housing assembly to the trigger guard mount assembly where the light housing contains a laser light source or a light bulb. A dovetail is formed on the trigger guard mount base to engage a dovetailed slot on the light housing, where the dovetailed slot is adjustable in width for releasably capturing the dovetail of the trigger guard mount base. The trigger guard mount assembly also includes set screws for fixing the trigger guard mount assembly in position on the forward portion of the trigger guard of the firearm. One or more shims are contained within the groove of the trigger guard mounting assembly.

Abstract: A configurable I/O arrangement for a controller has a number of internal and external input/output terminals, each of which are field selected as either an input or an output terminal. Logic functions of the controller are configured for a number of output terminals using up to 32 internal logical states and the states of 32 external physical I/O points. The update timing for each logic circuit is selectable to be synchronized in several different ways: synchronous with an internal event within the controller, synchronous with an event external to the controller, and asynchronous. The I/O arrangement includes a combination of a synchronous latchable input state array, user configurable means for logically combining the output signals of the reading circuits, and means for actuating external devices as a function of the logical combinations of the output signals of the reading circuits.

Abstract: A printed circuit board layout is provided for minimizing signal delays caused by mismatch in length of the inner leads of a package lead frame. This is accomplished by the provision of a unique conductive trace pattern formed preferably on the top surface or else on a lower surface of an electrically-insulated, heat-conducting printed circuit board. The conductive trace pattern includes a plurality of U-shaped metallized traces. Each of the plurality of U-shaped traces have a varying length so that certain ones adjacent the inner leads at the center of the package lead frame are longer than certain ones adjacent the inner leads at the corners of the package lead frame. The conductive trace pattern and the outer leads of the package lead frame also serve to transfer heat away from a molded-plastic body encapsulating an integrated-circuit die and the package lead frame and distribute the same on the printed circuit board.

Abstract: A tape measurement apparatus is provided for measuring the slope height of a GPS surveying system receiver, with an integral antenna, which is vertically suspended over a ground mark. A tape mounting hook is provided for securing the distal end of a tape measure in a location which is known precisely with respect to the phase center of the GPS receiver. The tape measure housing has a pointer arm of precisely known length which extends out from the tape measure housing in a direction opposite and parallel to the normalized line of extension of the tape from the housing. A distance scale imprinted on the tape compensates for the combined lengths of the housing and pointer arm so that a user can read the uncorrected slope height of the GPS receiver directly from the scale while applying the tip of the pointer arm to the ground mark.

Abstract: A leadframe ball grid array package for packaging an integrated-circuit die includes a metallic substrate having a central portion and a leadflame having a plurality of inwardly-extending bonding fingers and a centrally-located open portion. The leadframe is directly attached to the metallic substrate by a non-conductive adhesive so that the open portion thereof overlies the central recessed portion of the metallic substrate. An integrated-circuit die is mounted in the central portion of the metallic substrate. The bonding fingers are disposed peripherally surrounding the integrated-circuit die. Bonding wires are interconnected between bonding pads formed on the integrated-circuit die and the plurality of bonding fingers. A solder mask is disposed over the top surface of the leadframe so as to form selective solderable areas. Solder balls are attached to the selective solderable areas. A plastic material or a lid is applied over the top surface of the die, bonding fingers and bonding wires.

Abstract: An apparatus for securing a GPS data collector to a range pole includes an elongated base plate. The base plate has sidewalls, retaining wings, at least one first tab resiliently mounted perpendicularly to the base plate, at least one bottom support lip extending normally upward from the bottom of the base plate, and at least one second tab mounted to the bottom support lip and extending upward parallel to the base plate. Each of the tabs are adapted to engage a corresponding slot in the lower end of a data collector and the wings constrain the head end of a data collector unit.

Abstract: A method and system for automatically collecting and for analyzing information about time and work performed on a computer includes the following elements: data collector means for monitoring certain portions of a user's computer activity; data collector means for logging into a log file those certain portions of a user's computer activity; data analyzer means for determining, by means of user-defined rules, which portions of those certain portions of a user's computer activity constitutes continuous work activities and how this work should be categorized by project and task with project; and external interface means for building the rules defining work. The data collector means for monitoring certain portions of a user's computer activity includes a resident module, such as a TSR (terminate-and-stay-resident) module, which extends the file system of the computer so that detailed records are kept of file activities.

Abstract: A package for an integrated-circuit includes a package body having a die-cavity formed therein. A die-attach pad is formed in the package body adjacent the die-cavity. An opening is formed in the central portion of the die-attach pad for exposing one side of the integrated-circuit die so that an external cooling media can directly contact the exposed side of the integrated-circuit die. The die-attach pad can be formed as a die-mounting ring adjacent the die-attach cavity. The peripheral edge of the integrated-circuit die is fixed to a mounting surface on the die-mounting ring portion to accommodate direct cooling of the exposed side of the integrated-circuit die. The mounting surface of the die-mounting ring extends beyond the peripheral edge of the integrated-circuit die to accommodate a range of sizes of the integrated-circuit die.

Abstract: A multi-layer substrate structure and a method for fabricating the same are provided. Thin metal foils are laminated on the top and bottom sides of a non-conductive layer so as to form a laminated substrate. A plurality of plated-through holes are formed in the laminated substrate and are then filled with an epoxy. The laminated substrate is then patterned and etched. Epoxy layers are disposed on both sides of the laminated substrate. The laminated substrate is formed with a plurality of smaller plated-through holes extending through the epoxy layers and with a cavity to receive an integrated-circuit die. The through holes and the epoxy layers are metallized on both sides of the laminated substrate. The laminated substrate is patterned and etched again. A solder mask is applied on both sides of the laminated substrate so as to form selective wire bondable areas and selective solderable areas. The integrated circuit die is disposed in the center of the cavity and has a plurality of bonding pads.

Abstract: A GTL input receiver for receiving differential GTL signals and for generating a CMOS output at a single-ended output terminal includes a comparator circuit, a current-to-voltage converter circuit, and an inverter. The comparator is formed of a first primary current steering device and a second primary current steering device. Auxiliary current steering devices are coupled to the first and second primary current steering devices for adding hysteresis by dynamically changing the ratio of the currents flowing through the first and second primary current source devices. The input receiver also includes a control circuit for selectively enabling and disabling the secondary current steering devices. As a result, the GTL input receiver has a hysteresis in the range of 50 mV to 200 mV and higher.

Abstract: For negative gate erase and programming of non-volatile floating gate EEPROM devices, large positive or negative voltages from one single negative charge pump and from one single positive charge pump are selectively switched onto a one or more memory sectors of twin-well CMOS negative-gate-erase memory cells. The control gate is negative during erasing and positive during programming. In order for FLASH memories to have minimum layout area, small sectors or arrays of EEPROM cells can be erased all at once using a charge pump which includes two pump capacitors to provide negative voltages to the gate terminals of one or more series PMOS transistors.

Abstract: A quad flat pack arrangement which provides for an electrically enhanced integrated-circuit package structure is disclosed. An integrated-circuit die is centrally attached to the top surface of a thermally-conductive, and electrically conductive or insulated substrate. A lead frame having a plurality of inwardly-extending bonding fingers has the bottom sides thereof attached to the top surface of the substrate by a non-conductive adhesive so that an open portion thereof overlies the integrated-circuit die. The plurality of bonding fingers are disposed so as to peripherally surround the integrated-circuit die. A double-sided printed circuit board having first and second conductive layers disposed on its opposite sides is disposed over and bonded to the lead frame. Bonding wires are used to interconnect bonding pads on the integrated-circuit die to the first and second conductive layers. A plastic material is molded around the substrate, die, lead frame, printed circuit board and conductive layers.

Abstract: The technique of redundantly retransmitting digitized voice data on multiple sequential frequencies increases the channel bit rate above the minimum required for normal communication in a frequency-hopping communication system for digitized voice signals. Digitized voice data is redundantly retransmitted on multiple sequential frequencies and the channel bit rate is increased above the minimum required for normal communication. Repeated transmissions of the same block of digitized voice data occurs n times at n times the bit rate of the original digitized voice data. A frequency-hopping transmitter transmits on different channels, or carrier frequencies, which are modulated by the digitized voice data signals from a transmitter data buffer. A receiver data buffer holds n blocks of digitized voice data.

Abstract: An impedance probe circuit and method presents a balanced load to a DC or RF voltage source and to two voltage measurement nodes. The impedance probe circuit is accurate for measurement of an impedance device X which has a range always less than the value of a characteristic impedance C. A source terminal is coupled to a voltage source having a series impedance C. A test resistor T is connected between the source terminal and one terminal X1 the unknown impedance. A reference resistor R is connected between the source terminal and the other terminal X2 of the unknown impedance. The parallel combination of the test resistor T and the reference resistor R has an impedance substantially equal to C/3. A third impedance of value C/3 is connected to the node X1 and to a first voltage measurement terminal. A fourth impedance of value C/3 is connected to the node X2 and to a second voltage measurement terminal.

Abstract: A compact rf reader apparatus integrated into a single compact package structure. In one embodiment, a rotatably adjustable head is mounted on the compact reader body portion containing read/write electronics and an interface controller. The rotatably adjustable head contains an antenna and is adapted to direct the antenna in numerous different directions without moving the compact reader body portion of the rf reader. Additionally, in one embodiment, the rf reader unit includes a switching power supply located within the reader body portion. The switching power supply is electrically coupled to the read/write electronics and the interface controller, and is synchronized with the transmitting frequency of the antenna to prevent interference.

Abstract: A position-related multi-media presentation system for a vehicle. A position determining system generates position information of a vehicle. The position information is transferred to a multi-media system. The multi-media system presents information related to the position of the vehicle to an occupant of the vehicle. In one embodiment, video information is displayed on a display unit located on the back of a seat of an aircraft. The video information provides views related to features over which the aircraft is flying.

Abstract: An improved charge pump circuit uses standard low-voltage fabrication process for programming an anti-fuse memory cell from a high-voltage current source. A column-selection transistor which has a gate terminal connected to a control terminal. The column-select transistor is connected between a high voltage programming current source and one terminal of an anti-fuse link. The other terminal of the anti-fuse link is connected through a word-selection transistor to ground. The gate terminal of the word-selection transistor is connected to a word selection line. Two oppositely phased charge pumps provide a boosted voltage. A trapping-diode-connected transistor isolates the boosted voltage from the gate terminal of the column-selection transistor. A charge-kicker circuit further boosts the voltage on the gate of the column-selection transistor to turn on and pass current from the high voltage programming current source through the anti-fuse link.