Abstract: A method for minimizing signal delays caused by mismatch in length of the inner leads of a package lead frame. This is accomplished by the provision of a unique conductive trace pattern formed preferably on the top surface or else on a lower surface of an electrically-insulated, heat-conducting printed circuit board. The conductive trace pattern includes a plurality of U-shaped metallized traces. Each of the plurality of U-shaped traces have a varying length so that certain ones adjacent the inner leads at the center of the package lead frame are longer than certain ones adjacent the inner leads at the corners of the package lead frame. The conductive trace pattern and the outer leads of the package lead frame also serve to transfer heat away from a molded-plastic body encapsulating an integrated-circuit die and the package lead frame and distribute the same on the printed circuit board.

Abstract: A semiconductor integrated circuit package is provided with insulated bonding wires. The semiconductor die is mounted to a base of either a leadframe or a grid-array package. A plurality of bonding wires are bonded between bonding pads on the semiconductor die and bonding fingers at inner ends of package conductors. The bonding wires have an oxygen-plasma oxide formed thereupon to thereby provide electrically-insulated bonding wires to prevent short-circuits between adjacent bonding wires. After wire bonding of the bonding wires, the bonding wires are subjected to an oxygen plasma to form an insulating oxide on the bonding wires to prevent short-circuits with adjacent wires. The wires are aluminum or copper with an oxygen-plasma oxide formed thereupon. An oxygen-plasma oxide is simultaneously formed on a leadframe and is removed from the outer ends of the leads by blasting with a medium.

Abstract: A semiconductor integrated circuit package is provided with insulated bonding wires. The semiconductor die is mounted to a base of either a leadframe or a grid-array package. A plurality of bonding wires are bonded between bonding pads on the semiconductor die and bonding fingers at inner ends of package conductors. The bonding wires have an oxygen-plasma oxide formed thereupon to thereby provide electrically-insulated bonding wires to prevent short-circuits between adjacent bonding wires. After wire bonding of the bonding wires, the bonding wires are subjected to an oxygen plasma to form an insulating oxide on the bonding wires to prevent short-circuits with adjacent wires. The wires are aluminum or copper with an oxygen-plasma oxide formed thereupon. An oxygen-plasma oxide is simultaneously formed on a leadframe and is removed from the outer ends of the leads by blasting with a medium.

Abstract: A semiconductor integrated circuit package is provided with insulated bonding wires. The semiconductor die is mounted to a base of either a leadframe or a grid-array package. A plurality of bonding wires are bonded between bonding pads on the semiconductor die and bonding fingers at inner ends of package conductors. The bonding wires have a PECVD S.sub.i O.sub.2 layer formed thereupon to thereby provide electrically-insulated bonding wires to prevent short-circuits between adjacent bonding wires. After wire bonding of the bonding wires, an insulating PECVD S.sub.i O.sub.2 layer is formed on the bonding wires to prevent short-circuits with adjacent wires. An S.sub.i O.sub.2 layer is simultaneously formed on a leadframe and is removed from the outer ends of the leads by blasting with a medium.

Abstract: A die-down HBGA package includes an integrated-circuit die mounted to a substantially flat lower surface of a die-carrier/heat spreader. A flexible insulated tape layer with a central opening for the die has its upper surface adhesively fixed to the lower side of the die-carrier/heat spreader. Wire-bonding sites and a number of contact areas are connected by traces on the lower surface of the tape layer. Bonding-wire loops are connected between the wire-bonding pads on the die and the wire-bonding sites on the insulated tape layer. A rigid board, such as an epoxy or ceramic circuit board, with electrically conductive plated-through holes is fixed to the insulated flexible tape layer with adhesive. Conductive adhesive material connects the contact areas with the top surfaces of the plated-through holes. Alternatively, pins join the carrier/heat spreader and the rigid circuit board. Solder pads for solder balls are formed on the bottom surface of the printed-circuit board.

Abstract: A flash memory EEPROM device with a programming current limiting ability operates with six terminals and includes a source-side injection cell and a current limiter in series with the cell at a source region of the cell. During programming, an upper current limit is established for the overall channel current through the cell by controlling the voltage on a serial-gate of the current limiter. A second embodiment of a flash memory EEPROM device is structured with only four operating terminals, and includes a current limiting transistor integrally merged with a source-side injection cell. Merger is accomplished by eliminating the source junction of the injection cell and by combining the select-gate of the injection cell with the serial-gate of the current limiting transistor to create a conjoint select-gate. The unified channel under the conjoint select-gate consists of two channel sub-sections with different threshold adjustment implants and thus different threshold voltages.

Abstract: An apparatus and method for balancing the flow of molten molding compound above and below an integrated circuit assembly during encapsulation of the assembly. An annular shaped layer of material is placed over the bonding fingers of a leadframe such that the annular shaped layer of material peripherally surrounds the centrally located opening in the leadframe. The annular shaped layer of material has sufficient width and thickness to slow the flow of molten molding material over the top surface of the integrated circuit assembly to the same speed as the flow of molten material under the bottom surface of the integrated circuit package assembly. In so doing, the present invention reduces the formation of blowholes or voids in encapsulated integrated circuit packages.

Abstract: A processor is provided for an improved semiconductor etching system which generates a series of multi-bit digital output code words. The processor provides an endpoint detector for determining if one of the digital output code word has reached a predetermined endpoint level and for generating a control signal to stop etching of a wafer. The processor further provides a standard endpoint curve corresponding to standard etching of a standard wafer. A normalizer is provided for normalizing the current endpoint curve generated from the series of multi-bit digital code words for a wafer being etched with respect to the standard endpoint curve and for providing a normalized current endpoint curve.

Abstract: A method and system for automatically collecting and for analyzing information about time and work performed on a computer network which includes the following elements: a data collector for monitoring certain portions of a user's computer network activity and for logging into a log file those certain portions of a user's computer network activity; a data analyzer for determining by following user-defined rules showing which portions of those certain portions of a user's computer network activity constitutes continuous work activities, and how this work should be categorized by project and task with project; and an external interface for building the rules defining work. The data collector includes a resident module, such as a TSR (terminate-and-stay-resident) module, which extends the file system of the computer so that detailed records are kept of file activities.

Abstract: An adjustable duty-cycle circuit includes an EXCLUSIVE-OR circuit for combining a divided reference input signal at a frequency .function..sub.IN /2 with a variably delayed divided reference input signal to provide an output frequency V.sub.O at .function..sub.IN with an adjustable duty cycle. A variable delay circuit, or delay line, is controlled by a control signal which is generated by comparing a signal equal to the average (DC) value of V.sub.O with an adjustable DC reference signal from a voltage divider or a DAC. An output signal from the comparator is filtered to provide the control signal V.sub.C for the delay circuit to control the duty cycle of the output signal. To provide a frequency doubler, the reference input signal is not divided by two to thereby obtain an output signal at 2.function..sub.IN with an adjustable duty cycle. Frequency multipliers for N=3, 5, 7, etc. are implemented with additional delays and exclusive logic circuits.

Abstract: A range pole and in-line detachable battery module assembly including a range pole (10) with an elongated tubular graphite-epoxy range pole shell (102) which has a female cap assembly (108) and a male cap assembly (26) at opposite ends. The male cap assembly (26) includes a central bore (30) formed therethrough for containing an insulator plug (32) to which are attached coaxial electrical contacts (132, 134). The coaxial electrical contacts include a first contact surface surrounded by a second concentric contact surface. The male cap assembly includes an externally threaded stud (28) having a central bore (30) formed therethrough for containing an insulator plug (32) to which are attached pin sockets (67, 68) which contain spring-loaded male pin electrical contacts (34, 36). A detachable battery module (12) includes a tubular battery-module shell (24) which has a male cap (26) at one end.

Abstract: A wrist-strap monitoring system includes a first wrist-strap monitoring circuitry and a second wrist-strap monitoring circuitry. The first wrist-strap monitoring circuitry is used to monitor continuously impedance of a first human body to be between an upper level and a lower level. The second wrist-strap monitoring circuitry is used to monitor continuously impedance of a second human body to be between the upper level and the lower level. A logic circuit is responsive to the first and second wrist-strap monitoring circuitry for generating an alarm signal. A sound device is responsive to the alarm signal for generating an audible signal. Further, there is provided a ground detection circuit operatively connected to a ground connection for monitoring continuity of the ground connection.

Abstract: An overhead truck rack is provided for a pickup truck which includes four one-piece corner brackets to each of which are fastened: one end a longitudinal rail, one end of a lateral rail, and an upper end of a leg. A corner bracket includes a horizontally disposed, one-piece, cantilevered top crosspiece to which is fastened one of the pair of longitudinal rails. Each of the corner brackets also includes two integral, spaced-apart side panels which downwardly depend from the top crosspiece. Between the spaced-apart side panels are positioned an end of one of the lateral rails and between the spaced-apart side panels is pivotably mounted an upper end of one of the legs to allow for lateral movement of the lower end of the legs to allow for adjustment of the lateral spacing of the lower ends of the legs. The lower ends of the legs are connected to respective brackets at respective mounting points on the body of the pickup truck.

Abstract: A read only memory including: a plurality of memory cells arranged in x rows and y columns in an array; x wordlines each connected to y memory cells in a respective row; y bitlines each associated with x memory cells in a respective column; m reference bitlines each corresponding to n bitlines, each of the reference bitlines having x reference cells each connected to a respective wordline; and m sense amplifiers each having a first input terminal connected to a respective n bitlines and having a second input terminal connected to one of the reference bitlines, and each being responsive to a difference between a signal on one of the n bitlines and a signal on one of the reference bitlines.

Abstract: A row identification circuit identifies which redundant-row fuse has been blown in a memory integrated-circuit by electrically interrogating the integrated-circuit using a switching circuit internal to the memory integrated-circuit. N data output terminals of the memory integrated circuit provide an n-bit binary-coded word which identifies a defective row. To bring out the binary fuse data, the chip is put into a test mode with a TESTF signal which shuts off a normal CMOS transmission gate as well as a latch feedback transmission gate and which turns on another CMOS transmission gate to pass a defective row address bit FUSEB to a data output terminal for the memory device. A switching circuit selectively switches either a defective row address bit TESTB or a data input signal DIN to a data output terminal of the memory integrated circuit. The switching circuit is selectively controlled by a test mode control signal TESTF.

Abstract: A taximeter system includes a taximeter or trip meter for a truck integrated with an integral GPS receive/computer for providing GPS position and time information. The odometer input pulses to the taximeter are accurately calibrated by using GPS position, velocity, and time information to generate corrected odometer pulses which are provided to the odometer input terminal of the taximeter. The GPS system is integrated into the taximeter for calibrating and cross checking of input odometer pulses to provide reliable, consistent distance measurements by the taximeter. The integrated taximeter and GPS system provided according to the invention uses GPS position, velocity, and time information to produce incontrovertibly accurate corrected, odometer input pulses and GPS time signals for the taximeter to precisely compute elapsed time and distance traveled. Dead reckoning operation of the system is available when the GPS receiver has service outages.

Abstract: A control circuit initiates operation of the ROM array and the RAM array in an ATD circuit includes an EXCLUSIVE NOR circuit having: a RAM SELECT input terminal for receiving a RAM SELECT (RAMCS*) signal, a ROM SELECT input terminal for receiving a ROM SELECT (ROMCS*) signal, and having a chip enable output terminal at which is provided a chip enable signal (CE) at an active LOW state whenever the RAMCS* and the ROMCS* are both the same logic level, both either HIGH or LOW. The control circuit further includes a compensating pulse circuit to compensate for operation of the EXCLUSIVE NOR circuit during a dead-time interval in which the EXCLUSIVE NOR circuit does not function when the RAMCS* and the RAMCS* both change during that dead-time interval. The compensating circuit includes a two pulse generators, each generating an output pulse having a pulse width which is greater than the dead-time interval of the EXCLUSIVE NOR circuit.

Abstract: An integrated-circuit die is attached to the top interior surface of a die-cavity formed in the underside of a heat spreader. The other side of the integrated circuit die has a number of wire-bonding pads formed thereupon. A plurality of bonding-wire loops at least some of which are completely contained within the die-cavity to allow the part of the encapsulation or lid to be as thin as possible, while still covering the bonding wires. A first portion of a insulated tape layer covers the lower outside surface of the die-carrier/heat spreader and another portion of the insulated tape layer extends inside of the die-cavity and has a number of wire-bonding sites formed thereupon. A plurality of bonding-wire loops are bonded to one of the wire-bonding pads formed on the integrated-circuit die and the wire-bonding sites formed on the insulated tape layer.

Abstract: A method and apparatus for a reinforced leadframe to substrate attachment in a semiconductor assembly. In one embodiment, a printed circuit board having a plurality of electrically coupled electrical contact regions and wire bond areas formed thereon has a leadframe attached thereto such that each of the bonding fingers of the leadframe is coupled to a respective electrical contact region on the printed circuit board. A ribbon of B-staged epoxy is disposed on the leadframe such that the leadframe is disposed between the ribbon of B-staged epoxy and the printed circuit board. An integrated-circuit die is mounted on the printed circuit board with the bonding fingers of the leadframe peripherally surrounding the integrated circuit die. The bonding pads on the integrated-circuit die are electrically coupled to respective wire bond areas on the printed circuit board.

Abstract: A resettable latch circuit provides a modified address transition detection (XATD) signal in response to receiving an address-change input pulse signal at a SET input terminal thereof. A RESET input terminal for the latch circuit receives a delayed reset signal from a resettable delay circuit which has its input terminal coupled to the output terminal of the resettable latch circuit to receive the XATD signal. The resettable delay circuit includes a reset control signal terminal to which is coupled an inverted address-change input pulse. One embodiment of the resettable delay circuit includes a series of inverters and MOSFET load resistors as well as shunt MOSFET transistors turned on by the address-change signal to shunt the output terminals of the inverters and reset the delay line. The SET input terminal of the latch circuit also receives a chip-select-change signal pulse which is similar to the address-change pulse.