Patents Represented by Attorney Patterson and Sheridan, LLP
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Patent number: 8299466Abstract: Embodiments of the present invention generally relate to a TFT and a method for its fabrication. The TFT disclosed herein is a silicon based TFT in which the active channel comprises amorphous silicon. Over the amorphous silicon, multiple layers of doped silicon are deposited in which the resistivity of the doped silicon layers is higher at the interface with the amorphous silicon layer as compared to the interface with the source and drain electrodes. Alternatively, a single doped silicon layer is deposited over the amorphous silicon in which the properties of the single doped layer change throughout the thickness. It is better to have a lower resistivity at the interface with the source and drain electrodes, but lower resistivity usually means less substrate throughput. By utilizing multiple or graded layers, low resistivity can be achieved. The embodiments disclosed herein include low resistivity without sacrificing substrate throughput.Type: GrantFiled: October 28, 2010Date of Patent: October 30, 2012Assignee: Applied Materials, Inc.Inventors: Gaku Furuta, Soo Young Choi, Omori Kenji
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Patent number: 8299523Abstract: In general, according to one embodiment, a semiconductor device includes a first electrode, a first and a second semiconductor layer of a first conductivity type, a third semiconductor layer of a second conductivity type, a fourth semiconductor layer of the first conductivity type in this order. A device region includes a gate electrode inside a first trench. A second trench having a ring-shaped structure forms a first region penetrating through the fourth and third semiconductor layers to the second semiconductor layer and including the device region inside and a second region surrounding the first region outside. A first opening is provided between adjacent ones of the first trenches. A second opening having a wider width than the first opening is provided in the first region outside the device region. A second electrode is electrically connected to the third and fourth semiconductor layers through the first and second openings.Type: GrantFiled: August 1, 2011Date of Patent: October 30, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Kouta Tomita, Noboru Matsuda, Hideyuki Ura
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Patent number: 8301980Abstract: One embodiment of the present invention sets forth a technique for protecting data with an error correction code (ECC). The data is accessed by a processing unit and stored in an external memory, such as dynamic random access memory (DRAM). Application data and related ECC data are advantageously stored in a common page within a common DRAM device. Application data and ECC data are transmitted between the processor and the external common DRAM device over a common set of input/output (I/O) pins. Eliminating I/O pins and DRAM devices conventionally associated with transmitting and storing ECC data advantageously reduces system complexity and cost.Type: GrantFiled: September 28, 2009Date of Patent: October 30, 2012Assignee: NVIDIA CorporationInventors: Fred Gruner, Shane Keil, John S. Montrym
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Patent number: 8300147Abstract: A system and method for characterizing the relative offset in time between audio and video signals and enables the receiver of the audio and video signals to resynchronize the audio and video signals. Signal characterization data is dynamically captured and encoded into frames of video and audio data that is output by a television origination facility. The signal characterization data is extracted by the receiver and signal characterization data is captured for the received frames. The extracted signal characterization data is compared with the captured signal characterization data to compute the relative offset in time between the video and one or more audio signals for a frame. The receiver may then resynchronize the video and audio signals using the computed relative offset.Type: GrantFiled: June 2, 2010Date of Patent: October 30, 2012Assignee: Disney Enterprises, Inc.Inventors: Michael J. Strein, Efthimis Stefanidis, James L. Jackson
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Patent number: 8297417Abstract: A front bicycle suspension assembly having an inertia valve is described. The front bicycle suspension assembly may include at least upper and lower telescoping tubes and include a damping tube containing an inertia valve. The inertia valve may include an inertia mass movable along the outer surface of a valve shaft as the inertia valve moves between first and second positions.Type: GrantFiled: August 2, 2010Date of Patent: October 30, 2012Assignee: Fox Factory, Inc.Inventor: Robert C. Fox
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Patent number: 8300924Abstract: A tracker component for a computer vision engine of a machine-learning based behavior-recognition system is disclosed. The behavior-recognition system may be configured to learn, identify, and recognize patterns of behavior by observing a video stream (i.e., a sequence of individual video frames). The tracker component may be configured to track objects depicted in the sequence of video frames and to generate, search, match, and update computational models of such objects.Type: GrantFiled: September 11, 2008Date of Patent: October 30, 2012Assignee: Behavioral Recognition Systems, Inc.Inventors: John Eric Eaton, Wesley Kenneth Cobb, Rajkiran K. Gottumukkal, Kishor Adinath Saitwal, Ming-Jung Seow, Tao Yang, Bobby Ernest Blythe
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Patent number: 8300351Abstract: According to one embodiment, a magnetic recording apparatus includes a magnetic recording medium for perpendicular magnetic recording system, a magnetic head including a read head to read data from the magnetic recording medium, and an actuator to actuate the magnetic head on the magnetic recording medium. The magnetic recording medium includes a first magnetic pattern recorded in a servo area by applying a magnetic field horizontally to a disk surface, and the first magnetic pattern corresponding to positioning data used for positioning the magnetic head. The magnetic recording medium further includes a second magnetic pattern recorded in the servo area by applying a magnetic field perpendicularly to the disk surface, and the second magnetic pattern corresponding to position correction data used for correcting the positioning data. The position correction data is derived from modulated original position correction data. The original position correction data is created for correcting the positioning data.Type: GrantFiled: June 23, 2011Date of Patent: October 30, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Hiroyuki Suzuki, Hiroshi Kubota, Masahide Yatsu
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Patent number: 8300647Abstract: A hash engine in a network device driver maintains data on the utilization and error rate for each network interface card (“NIC”) within a local computing device. From this data, the hash engine intelligently selects transmit NICs and receive NICs based on various networking parameters provided from a software driver program. Transmit packets sent from the operating system in a local computing device to a remote computing device are intercepted, modified and redirected to transmit NICs selected by the hash engine for transmission to remote computing devices. Similarly, address resolution protocol (“ARP”) response packets sent by the operating system in response to ARP request packets are intercepted, modified and redirected to receive NICs selected by the hash engine for transmission.Type: GrantFiled: May 18, 2007Date of Patent: October 30, 2012Assignee: NVIDIA CorporationInventors: Ayaz Abdulla, Norman K. Chen, Anand Rajagopalan, Ashutosh K. Jha, Hemamalini Manickavasagam, Sameer Nanda
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Patent number: 8298959Abstract: Embodiments of the invention relate to a substrate etching method and apparatus. In one embodiment, a method for etching a substrate in a plasma etch reactor is provided that includes a) depositing a polymer on a substrate in an etch reactor, b) etching the substrate using a gas mixture including a fluorine-containing gas and oxygen in the etch reactor, c) etching a silicon-containing layer the substrate using a fluorine-containing gas without mixing oxygen in the etch reactor, and d) repeating a), b) and c) until an endpoint of a feature etched into the silicon-containing layer is reached.Type: GrantFiled: May 24, 2010Date of Patent: October 30, 2012Assignee: Applied Materials, Inc.Inventor: Alan Cheshire
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Patent number: 8301894Abstract: A method (100) and a system (300) for applying digital signatures (206, 216, and 222) to translated content (and other content) can include a presentation (309) and a user interface presented on the presentation device. The system can further include at least one processor (307) that operates to create (102) the user interface in a first language as part of an application, enables (104) the entering of data into the user interface and the digital signing of the data by a first user, translates (106) the user interface to at least a second language, and presents (108) the data to at least a second user using the application. A recipient device can verify (110) the digital signatures where a verification of the digital signatures independently verifies a data signature (222), a user interface signature (206), and a translated user interface signature (216).Type: GrantFiled: January 10, 2008Date of Patent: October 30, 2012Assignee: International Business Machines CorporationInventor: Wayne Malkin
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Patent number: 8295621Abstract: A system and method uses the capabilities of a geometry shader unit within the multi-threaded graphics processor to offload data compression computations from a central processing unit (CPU), reduce the memory needed to store image data, and reduce the bandwidth needed to transfer image data between graphics processors and between a graphics processor and a system memory. The multi-threaded graphics processor is also configured to perform decompression of the variable length compressed data using the geometry shader unit.Type: GrantFiled: December 13, 2007Date of Patent: October 23, 2012Assignee: NVIDIA CorporationInventor: Franck R. Diard
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Patent number: 8296515Abstract: One embodiment of the present invention sets forth a technique for performing RAID-6 computations using simple arithmetic functions and two-dimensional table lookup operations. A set of threads within a multi-threaded processor are assigned to perform RAID-6 computations in parallel on a stripe of RAID-6 data. A set of lookup tables are stored within the multi-threaded processor for access by the threads in performing the RAID-6 computations. During normal operation of a related RAID-6 disk array, RAID-6 computations may be performed by the threads using a small set of simple arithmetic operations and a set of lookup operations to the lookup tables. Greater computational efficiency is gained by reducing the RAID-6 computations to simple operations that are performed efficiently on a multi-threaded processor, such as a graphics processing unit.Type: GrantFiled: December 16, 2009Date of Patent: October 23, 2012Assignee: Nvidia CorporationInventors: Nirmal Raj Saxena, Mark A. Overby, Andrew Currid
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Patent number: 8293015Abstract: Embodiments of the invention provide apparatuses and methods for atomic layer deposition (ALD), such as plasma-enhanced ALD (PE-ALD). In some embodiments, a PE-ALD chamber is provided which includes a chamber lid assembly coupled with a chamber body having a substrate support therein. In one embodiment, the chamber lid assembly has an inlet manifold assembly containing an annular channel encompassing a centralized channel, wherein the centralized channel extends through the inlet manifold assembly, and the inlet manifold assembly further contains injection holes extending from the annular channel, through a sidewall of the centralized channel, and to the centralized channel.Type: GrantFiled: September 14, 2011Date of Patent: October 23, 2012Assignee: Applied Materials, Inc.Inventors: Hyman W. H. Lam, Bo Zheng, Hua Ai, Michael Jackson, Xiaoxiong Yuan, Hougong Wang, Salvador P. Umotoy, Sang Ho Yu
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Patent number: 8293328Abstract: A method for depositing a refractory metal nitride barrier layer having a thickness of about 20 angstroms or less is provided. In one aspect, the refractory metal nitride layer is formed by introducing a pulse of a metal-containing compound followed by a pulse of a nitrogen-containing compound. The refractory metal nitride barrier layer provides adequate barrier properties and allows the grain growth of the first metal layer to continue across the barrier layer into the second metal layer thereby enhancing the electrical performance of the interconnect.Type: GrantFiled: September 7, 2006Date of Patent: October 23, 2012Assignee: Applied Materials, Inc.Inventors: Ling Chen, Hua Chung, Barry L. Chin, Hong Zhang
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Patent number: 8293430Abstract: Methods for fabricating a photomask are disclosed herein. In one embodiment, a method for fabricating a photomask includes providing a filmstack having a molybdenum layer and a light-shielding layer in a processing chamber, patterning a first resist layer on the light-shielding layer, etching the light-shielding layer using the first resist layer as an etch mask, and etching the molybdenum layer using the patterned light-shielding layer and the patterned first resist layer as a composite mask.Type: GrantFiled: January 27, 2005Date of Patent: October 23, 2012Assignee: Applied Materials, Inc.Inventors: Madhavi Chandrachood, Ajay Kumar, Wai-Fan Yau
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Patent number: 8294148Abstract: The present invention generally comprises TFTs having semiconductor material comprising oxygen, nitrogen, and one or more element selected from the group consisting of zinc, tin, gallium, cadmium, and indium as the active channel. The semiconductor material may be used in bottom gate TFTs, top gate TFTs, and other types of TFTs. The TFTs may be patterned by etching to create both the channel and the metal electrodes. Then, the source-drain electrodes may be defined by dry etching using the semiconductor material as an etch stop layer. The active layer carrier concentration, mobility, and interface with other layers of the TFT can be tuned to predetermined values. The tuning may be accomplished by changing the nitrogen containing gas to oxygen containing gas flow ratio, annealing and/or plasma treating the deposited semiconductor film, or changing the concentration of aluminum doping.Type: GrantFiled: July 26, 2011Date of Patent: October 23, 2012Assignee: Applied Materials, Inc.Inventor: Yan Ye
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Patent number: 8291857Abstract: Embodiments of the invention provide apparatuses and methods for atomic layer deposition (ALD), such as plasma-enhanced ALD (PE-ALD). In some embodiments, a PE-ALD chamber is provided which includes a chamber lid assembly coupled with a chamber body having a substrate support therein. In one embodiment, the chamber lid assembly has an inlet manifold assembly containing an annular channel encompassing a centralized channel, wherein the centralized channel extends through the inlet manifold assembly, and the inlet manifold assembly further contains injection holes extending from the annular channel, through a sidewall of the centralized channel, and to the centralized channel.Type: GrantFiled: June 30, 2009Date of Patent: October 23, 2012Assignee: Applied Materials, Inc.Inventors: Hyman Lam, Bo Zheng, Hua Ai, Michael Jackson, Xiaoxiong (John) Yuan, Hou Gong Wang, Salvador P. Umotoy, Sang Ho Yu
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Patent number: 8294115Abstract: A linear plasma electron source is provided. The linear plasma electron source includes a housing acting as a first electrode, the housing having side walls a slit opening in the housing for trespassing of a electron beam, the slit opening defining a length direction of the source, a second electrode being arranged within the housing and having a first side facing the slit opening, the first side being spaced from the slit opening by a first distance, wherein the length of the electron source in the length direction is at least 5 times the first distance, and at least one gas supply for providing a gas into the housing.Type: GrantFiled: November 17, 2008Date of Patent: October 23, 2012Assignee: Applied Materials, Inc.Inventors: Guenter Klemm, Volker Hacker, Hans-Georg Lotz
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Patent number: 8296658Abstract: A graphical user interface includes a primary color palette including a first plurality of colors and a secondary color palette including a second plurality of colors. A first color is defined as a primary color and a second color is defined as a secondary color. The secondary color is different from the primary color. The graphical user interface also includes a plurality of styles, with a style defined as an initial style. The graphical user interface further includes an intensity scale ranging from a minimum intensity value to a maximum intensity value. An indicator is positioned in association with an initial intensity value. Moreover, the graphical user interface includes a display tile including an initial pattern that is displayed based on the primary color, the secondary color, and the initial style and a subsequent pattern that is modified from the initial pattern based on the initial intensity value.Type: GrantFiled: September 19, 2008Date of Patent: October 23, 2012Assignee: Cisco Technology, Inc.Inventors: Jonathan Kaplan, Ariel Braunstein
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Patent number: 8294821Abstract: A software or hardware agent running on a personal computing device provides allows application programs to interact with consumer electronic devices using standardized controls. The consumer electronic devices appear to be directly connected to the personal computing device rather than being connected over a high definition multimedia interface (HDMI) network. This enables a user to control the consumer electronic devices using a single interface rather than a separate interface for each consumer electronic device. The agent enumerates a universal serial bus (USB) human interface device (HID) for each consumer electronic device reported on the HDMI network. The USB HIDs represent the specific capabilities of the each one of the consumer electronic devices.Type: GrantFiled: November 13, 2007Date of Patent: October 23, 2012Assignee: NVIDIA CorporationInventors: Mark A. Overby, Robert William Chapman