Abstract: A device and method for regulating the output of a power circuit is provided, which in one embodiment includes a pulsewidth modulation (PWM) circuit that produces pulses each having a period of at least a minimum duration, a comparator circuit that produces a control signal, a timer initiated at the output of each pulse and operable to expire no later than expiration of twice the minimum pulsewidth duration, and wherein the PWM circuit is operable to reduce the frequency of outputted pulses in response to receiving the control signal having a first state at expiration of the first timer initiated at the output of a first pulse.

Abstract: In an embodiment, a circuit includes a first transistor having a first current electrode, a control electrode, and a second current electrode coupled to a power supply terminal. The circuit further includes a resistive element having a first terminal coupled to the control electrode of the first transistor and a second terminal coupled to the power supply terminal. The circuit also includes a feedback circuit for providing a first current to the first control electrode of the first transistor and for preserving substantially the first current related to a voltage at the control electrode of the first transistor, through the resistive element. The feedback circuit includes an output terminal for providing an output signal in response to a voltage at the control electrode of the first transistor. In an embodiment, the first transistor is a floating-gate device with programmable threshold voltage.

Abstract: An over-power compensation circuit for use in a switched mode power supply having a current sense circuit for sensing a current flowing through a power transistor of the switched mode power supply. The over-power compensation circuit includes a peak detector, a sample-and-hold circuit, a current offset generator, and an offset resistor. The peak detector has an input for receiving an input voltage derived from the input line, and an output. The sample-and-hold circuit has an input connected to the output of the peak detector, and an output. The current offset generator has an input connected to the output of the sample-and-hold circuit, and an output for providing an offset current. The offset resistor has a first terminal connected to the output of the current offset generator, and a second terminal adapted to be connected to a current conducting electrode of the power transistor.

Abstract: A low dropout voltage regulator includes an error amplifier, a voltage divider, and a voltage reference/amplifier circuit. The error amplifier has first and second input terminals, a power supply terminal for receiving an input voltage, and an output terminal for providing a regulated output voltage. The voltage divider provides a feedback voltage as a predetermined fraction of said regulated output voltage. The voltage reference/amplifier circuit provides a first voltage to said first input terminal of said error amplifier that varies inversely with variations of said feedback voltage, and provides a second voltage to said second input terminal of said error amplifier that varies by substantially the same amount over temperature as variations in said first voltage.

Abstract: A control circuit (120, 140) for a brushless direct current (DC) motor (160) includes a current drive circuit (140), a current loop regulator (122), and a commutation loop regulator (124, 126). The current drive circuit (140) is adapted to drive the brushless DC motor (160) in a first polarity or a second polarity selectively in response to a control signal, and senses a current through the brushless DC motor (160) to provide a current sense signal. The current loop regulator (122) varies a duty cycle of the control signal to regulate the current in response to the current sense signal, and regulates the polarity of the current based on a state of a polarity signal. The commutation loop regulator (124, 126) regulates a transition of said polarity signal in response to a comparison of a pre-commutation duty cycle value and a post-commutation duty cycle value.

Abstract: A speakerphone system (50, 70) implements automatic gain control (AGC) when it is in a talk mode. While in the talk mode, the speakerphone system (50, 70) applies a gain factor determined by conventional AGC techniques. The inverse of this gain factor is applied to the received signal to avoid the need to adapt the coefficients of an echo canceller, such as an acoustic echo canceller (AEC) (25), as the volume level changes. The speakerphone system (50, 70) determines whether it is in the talk, double-talk, or listen mode by adaptively changing energy thresholds which define these modes, in dependence on the distribution of ratios of the transmitted energy to received energy. The speakerphone system (50, 70) also varies a loop gain in dependence on the separation between the distribution of energy ratios in the talk mode and in the receive mode. This automatic loop gain adjustment ensures loop stability.

Abstract: A wideband CDMA handset (20) has a receiver (50) which simplifies initial sequence acquisition. The receiver (50) includes an efficient searcher receiver (54) which searches for long code mask sequences (LMS) using two correlators (80, 100). The searcher receiver (54) determines the complex conjugate of the output of the first correlator (80), and uses it to remove the phase ambiguity of the output of the second correlator (100). Thus the second correlator (100) is able to perform multiple correlations at the same time. The searcher receiver (54) coherently combines the output of the second correlator (100) to improve the reliability of the search decision.

Abstract: In the present invention, an ADSL system (10) identifies good bin as a bin capable of successfully transmitting data to a destination. A bad bin is identified as a carrier that is not capable of successfully transmitting data to the destination. A marginal bin is identified as a carrier that may be capable of transmitting data to the destination. The power to a bad bin is reduced and allocated to the marginal or good bin(s) to allow an increased bit rate. In another embodiment, the power to marginal bin is reduced and allocated to the good bin(s).

Abstract: A memory controller (42) controls accesses to a command-based memory device (43) such as a synchronous DRAM. The memory controller (42) uses an address comparator (45) for both base address matching and command generation. When the memory controller (42) detects an access to the memory device (43) and a control register bit is set, a state machine (56) causes the command to be written to the memory device (43). The memory controller (42) thus allows the memory device (43) to be accessed with little additional circuitry, and to be connected to higher order address bits to speed the access. Since the commands are detected by accesses to the same memory locations as reads and writes, the memory controller (42) avoids creating “holes” in the memory map.

Abstract: A data processing system includes a data processor (10) coupled to a memory system having a first memory, such as an L1 data cache (16), arranged with a second memory (such as an L2 cache) at a lower hierarchical level. The data processor (10) prefetches data elements of a vector into the first memory prior to processing such data elements. If a requested data element is not present in the first memory, a load request is issued to the second memory and to lower levels of the memory hierarchy until the requested data element is finally retrieved and stored in the first memory. The data processor (10) continues to prefetch subsequent data elements of the vector by considering the length of the data element and the stride of the vector. In one embodiment, the data processor (10) prefetches the vector into the first memory in response to a single data stream touch load (DST) instruction (100).

Abstract: A memory controller (42) supports a mode known as continuous page mode. The memory controller (42) is coupled to a pipelined internal bus and provides control signals to an external bus to control a memory such as a dynamic random access memory (DRAM) (43). The memory controller (42) compares the page portion of a next address to the page portion of the current address. If the addresses match, the memory controller (42) keeps the page open for the next cycle. However if the addresses do not match, or if the next address is not valid at this same point in time during the first access, the memory controller (42) closes the page during the first cycle. The memory controller (42) performs continuous page mode without incurring a penalty when the page is closed.

Abstract: A communications system includes multiple processors (14, 16) and a protocol timer (18). The protocol timer (18) controls the timing of events in the communications system and operates autonomously after it is loaded with initial instructions by one of the multiple processors (14, 16). The protocol timer (18) utilizes a frame event table (50) and a macro event table (46, 48) to trigger events and to generate interrupts of the multiple processors (14, 16). By allowing the protocol timer (18) to operate autonomously, the processors (14, 16) are relieved of timing control, and can be powered down when not in use, thus reducing power consumption of the communications system. Also, by using the protocol timer (18) to control the timing of events, software related errors and interrupt latencies are reduced.

Abstract: An oversampled analog-to-digital converter (ADC) (20) includes a sigma-delta modulator (21) with two decimation filters to provide minimum power consumption. The first decimation filter (30) converts the output of the sigma-delta modulator (21) to a slower intermediate frequency and performs a first part of the decimation function. The second decimation filter (40) converts the output of the first decimation filter (30) to the output frequency and performs a second part of the decimation function. The ADC (20) saves power by allowing some of the second part of the decimation function to be performed at the slower intermediate frequency. In one form, the first decimation filter (30) includes a finite impulse response (FIR) filter (32) and a down sampler (34). By using a suitable logic circuit (56), the FIR filter (32) can be implemented with only a small amount of circuit area and most of the FIR filter (32) can be operated at the slower intermediate frequency.

Abstract: A pipelined dual port integrated circuit memory (20) includes an array (21) of static random access memory (SRAM) cells, wherein each of the memory cells (80) is connected to a single word line (72) and to a single bit line pair (74, 76). Each port's access is performed synchronously with respect to a corresponding clock signal. The two clock signal signals are asynchronous with respect to each other. When access requests are received from both ports substantially simultaneously, an arbitration circuit (24) determines which port receives priority. The port which receives priority accesses the array (21) first. The arbitration circuit (24) ensures that substantially simultaneous access requests are serviced sequentially and occur within a single cycle of a corresponding clock signal.

Abstract: Accordingly, the present invention provides a method for synchronously accessing memory in order to improve the performance in systems which use memories with slower cores. A first address for a first memory access is provided during a first clock period. A first control signal to indicate an address phase of the first memory access is activated during the first clock period. A second control signal to indicate a data phase of the first memory access is activated during a second clock period subsequent to the first clock period. A first data element accessed by the first address is received during a third clock period immediately subsequent to the second clock period. A second address for a second memory access is provided during the third clock period. The first control signal indicating an address phase of the second memory access is activated during the third clock period.

Abstract: A voltage generation circuit (60, 62) is adapted to sense voltages on multiple windings (82, 84, 86) of a multi-phase brushless DC motor (22) during successive intervals of a rotation of the motor (22) in which the respective windings (82, 84, 86) are not being driven. The voltage generation circuit (60, 62) provides a different output voltage from the voltage used to drive the motor (22). In one embodiment, the voltage generation circuit (60, 62) includes a voltage boosting circuit (62) to increase the output voltage above the drive voltage. This voltage generation circuit (60, 62) may be advantageously combined with an electrically programmable read only memory (EPROM) (56) on a single integrated circuit chip. The voltage generation circuit (60, 62) generates the EPROM programming voltage without the need for a costly on-chip charge pump or off-chip DC-DC converter.

Abstract: A floating point unit (60) capable of executing projection instructions provides performance improvement in multiple precision floating point arithmetic. The projection instructions provide for obtaining partial sequences of numbers, products, and sums which have definite alignments and widths which a programmer can set. This allows very fast computation of both individual intermediate computations and final results. A range projection instruction (210, 410) builds a mask with an exponent from one source (230, 430) and a mantissa from another (240, 440). A project instruction (610) builds a result by masking (660) mantissa bits in a source operand after alignment (630) with a mask. Projection multiply (810), add (1000), and subtract instructions build results by masking (850, 1070) mantissa bits of unrounded partial results after alignment (830, 1020, 1040) with a mask.

Abstract: An equalizer (106, 146) for use in systems such as an asymmetric digital subscriber line (ADSL) transceiver (5) reduces the number of calculations required for updating the equalizer coefficients. The equalizer (106, 146) takes advantage of the substantially symmetrical phase and amplitude distortion of the signal constellation, which causes both the amplitude and the phase relationship of the calculated error term for each constellation point to be equal. Instead of performing a full complex multiplication, the equalizer (106, 146) uses some but not all of the product terms between the real and imaginary components of the calculated error term and the conjugate of the received data estimate in the coefficient update calculation. The result is then scaled to account for the missing terms. The resulting equalizer (106, 146) requires fewer calculations for coefficient updating.

Abstract: An instruction set interpreter and translator provides dynamic idiom recognition by use of a programmable hash table. Idioms are sequences of consecutive instructions that occur frequently during execution. Interpretive execution of such idioms is optimized to attain high performance. Idioms are recognized dynamically during interpretive execution. A programmable hash table is extended with entries corresponding to newly recognized idioms as their frequency of occurrence exceeds a threshold.

Abstract: An output buffer translates digital input signals which toggle between ground and V.sub.DDL to signals which toggle between ground and V.sub.DDH. The technology dielectric breakdown voltage limit is less than the magnitude of V.sub.DDH, such that use of a traditional output stage would subject transistors' dielectrics to voltages which exceed their dielectric breakdown limit, and would thus be damaged. Predrive circuits (40, 50) control output stage (70) transistors' (72, 78) gates, and voltage dropping circuits control output stage (70) transistors (74, 76). These control signals are generated specifically to maximize output stage transistor drive strengths, thereby minimizing output stage size. Output buffer functions when V.sub.DDL =V.sub.DDH, and its performance is V.sub.DDL independent. Temperature compensation is incorporated into the output buffer by deliberately offsetting temperature effects on output stage transistor drive strengths.