Abstract: A mixed signal processing system (22) includes digital (28) and analog (29) systems and is powered by a variable external voltage, such as a battery voltage. A voltage regulator (41) regulates the battery voltage to a nominal potential less than the battery voltage. The voltage regulator (41) provides the regulated voltage to a digital subsystem (51) of the digital system (28). A regulated charge pump (43) provides a voltage which is above the battery voltage and substantially constant due to regulation. The regulated charge pump (43) provides the regulated charge-pumped voltage to an analog subsystem (61) of the analog system (29) for better analog operation. A level shifter (44) equalizes signal levels between the digital (28) and analog (29) systems.

Abstract: A square-law clamping circuit (99, 120) sinks a current from an input/output terminal proportional to a square of a difference between a voltage thereon and a reference voltage. A first MOS transistor (130) has a source for receiving the reference voltage, a gate, and a drain coupled to its gate. A current source (134) coupled to the drain of the first MOS transistor (130) sources a predetermined current therefrom. A second MOS transistor (132) has a source providing the input/output terminal (100, 121), a gate coupled to the drain of the first MOS transistor (130), and a drain. A current sink (135) coupled to the drain of the second MOS transistor (132) sinks a current therefrom.

Abstract: A data processing system (20) having a burst address generator (BAG) 55, with a programmable transaction mode applicable to both cache and pre-fetch architecture types. BAG 55 asserts a data acknowledge (DTACK) signal to end a burst transfer on either a physical boundary, as in pre-fetch mode at the end of a row in a memory device, or a limit detection, as in cache mode where the limit is determined by the length of a cache line. BAG 55 increments the burst address internally, and for operations in pre-fetch mode, the user determines if the incremented address is provided external to data processor (22).

Abstract: A data processor (20) includes a firewall circuit (50) that monitors privilege level changes or transitions between privilege modes, such as from user mode and user space into supervisory or privileged mode and operating system space. The firewall circuit starts a timer (54) whenever a central processing unit (22) enters supervisor mode. If the timer (54) determines the passage of a predetermined time while the central processing unit remains continuously in supervisory mode without re-entering user mode, a predefined security policy is invoked. For example, the security policy may require at this point that the data processor (20) is to be reset. Different timer (54) time-out values and different security policies can be set for different types of privilege level changes. In one embodiment, a default time-out value provides protection for multiple types of privilege level changes.

Abstract: A floating-gate non-volatile memory (30) uses a relatively-low threshold voltage to define a programmed state. The memory (30) compensates for fast program cells by providing program pulses which increase in length and magnitude while the cells are being programmed. Between each program pulse the memory (30) determines whether selected cells have been adequately programmed. The memory (30) ceases applying the series of pulses to each cell when it has been adequately programmed. Thus the memory (30) avoids the over-program condition instead of compensating for it.

Abstract: A communications system 10 having an Asymmetric Digital Subscriber Line (ADSL) transceiver (24) is provided which may be configured either as a central office or a remote terminal in a system. The transceiver (24) operates in a listen/report idle state to report line activity to a host processor (22) prior to being configured as a central office or remote terminal. The host processor configures the transceiver (24) as a central office, remote terminal, or as otherwise specified based on the line activity.

Abstract: A data processor such as an integrated circuit microcontroller (10) includes a central processing unit (12), a system integration module (14), and on-chip peripherals (16, 24, 28, 30) commonly connected by an information bus (32). The microcontroller (10) supports transparent background mode operation by not only preserving the state of the central processing unit (12), but also the states of on-chip peripherals (16, 24, 28, 30). For example, a serial peripheral interface (16) has a status register (86) with some status bits which are cleared in normal mode by reading the status register (86). In background mode, reading the status register (86) does not cause the status bits to be cleared. The system integration module (14) has a control bit, known as the break clear flag enable (BCFE) bit, which selectively allows the states of the on-chip peripherals (16, 24, 28, 30) to be altered when the microcontroller is in background mode.

Abstract: A single-ended to differential converter (400, 500) has an input terminal (418, 518) which is adapted to be coupled to an inductance (412, 512). A first transistor (402, 502) which terminates an input signal received at the input terminal according to its transconductance has a first current electrode coupled to the input terminal. A second current electrode of the first transistor (402, 502) outputs one current of a differential output current. A second transistor (404, 504) has a control electrode coupled to the input terminal, a first current electrode coupled to a signal ground terminal, and a second current electrode for providing another current of the differential output current. Bias circuits bias the control electrodes of the first (402, 502) and second (404, 504) transistors to maintain the same DC currents through their current electrodes.

Abstract: A sense amplifier (10) senses data by sensing a differential current signal comprised of a current (I.sub.1) flowing in an input terminal (12) and a current (I.sub.2) flowing in a complementary input terminal (22). During the sensing process, the sense amplifier (10) generates a first current flowing in a first FET (17) in accordance with the current (I.sub.1) flowing through the input terminal (12) and a second current flowing in a second FET (27) in accordance with the current (I.sub.2) flowing through the complementary input terminal (22). Two cross coupled inverters (16, 26) compare the first current (I.sub.1) with the second current (I.sub.2) and generate a differential output voltage signal, thereby sensing the data.

Abstract: A data interleaving system (20) provides flexibility by performing the interleaving function in a high level controller (32) and a separate low level controller (34). The high level controller (32) receives commands to operate on a codeword basis, in which a codeword is made up of a plurality of symbols which are grouped into a programmable number of frames. The low level controller (34) operates under the direction of the high level controller (32) on a symbol-by-symbol basis. By separating the codeword level tasks from the symbol level tasks, the data interleaving system (20) is able to accommodate various ratios of the number of frames per codeword without significant complexity. An analogous data de-interleaving system (220) includes a high level controller (232) and a low level controller (234).

Abstract: A synchronous pipelined burst memory (20) achieves high speed by violating conventional pipelining rules. The memory (20) includes an address register (24) which latches a burst address during a first cycle of a periodic clock signal. The burst address is driven to an input of an asynchronous memory core (40), but output data from the asynchronous memory core (40) is not latched until a third cycle of the periodic clock signal which occurs after a second cycle of the periodic clock signal which is immediately subsequent to the first cycle. The memory (20) outputs successive data elements of the burst during consecutive cycles of the periodic clock signal to complete the burst cycle.

Abstract: A transceiver (5) for an asymmetric communication system such as asymmetric digital subscriber line (ADSL) includes a configuration register (71) defining operation at either a central office (CO) or a remote terminal (RT). The configuration register (71) includes a control bit (72) for selecting either CO or RT mode. The transceiver (5) includes a signal processing module (70) configured according to the state of the control bit (72). For example, a digital interface (70) converts transmit data into transmit symbols and converts received symbols into receive data. The digital interface (70) uses a large memory (158) as a buffer in the transmit path and a small memory (160) as a buffer in the receive path in CO mode. In RT mode, the digital interface (70) uses the small memory (160) in the transmit path and the large memory (158) in the receive path. The selective configuration allows a single integrated circuit to be used in both CO and RT equipment.

Abstract: A data processor (20) which flexibly encrypts data within different address ranges includes an encryption determination circuit (50) to monitor an address conducted on an internal address bus (22) and when the address is within certain predefined ranges, perform encryption or decryption of address and/or data. For example the encryption determination circuit (50) may be used to selectively enable a data encryption-decryption circuit (60). When the data encryption-decryption circuit (60) is disabled, data conducted on an internal data bus (23) becomes "cleartext", i.e., non-encrypted. In one embodiment, the data encryption-decryption is performed in partial dependence on the address itself, and the address conducted to the external address bus is itself selectively encrypted as well.

Abstract: A Schmitt trigger (30) operates at low power and low frequency and can be implemented in a small amount of surface area on an integrated circuit. Specifically, the Schmitt trigger (30) includes transistors (34, 40) that are implemented as long channel devices and operate in a linear region for providing resistive elements, and another pair of transistors (44, 46) that function as non-linear devices allowing a current through the Schmitt trigger (30) to provide both a reference and the switchpoints for the Schmitt trigger (30). These transistors also establish low current through the Schmitt trigger (30).

Abstract: A data processing system (20) having programmable chip select signal negation. A user programmable "NEGATE EARLY" value generates a chip select negation one bus cycle before the end of a transaction, giving an external device additional time to disconnect from the current bus cycle before the start of the next bus cycle. Early negation of a chip select signal provides an efficient method of interface with slower devices while providing adding functionality to the chip select signal.

Abstract: A data processor (40) keeps track of misses to a cache (71) so that multiple misses within the same cache line can be merged or folded at reload time. A load/store unit (60) includes a completed store queue (61) for presenting store requests to the cache (71) in order. If a store request misses in the cache (71), the completed store queue (61) requests the cache line from a lower-level memory system (90) and thereafter inactivates the store request. When a reload cache line is received, the completed store queue (61) compares the reload address to all entries. If at least one address matches the reload address, one entry's data is merged with the cache line prior to storage in the cache (71). Other matching entries become active and are allowed to reaccess the cache (71). A miss queue (80) coupled between the load/store unit (60) and the lower-level memory system (90) implements reload folding to improve efficiency.

Abstract: A data processing system (10) selectively weights a fuzzy logic rule in response to a single "REVW" software instruction. In response to the REVW instruction, the data processing system (10) fetches a set of fuzzy inputs associated with the fuzzy logic rule, and determines a minimum fuzzy input from the set. The data processing system (10) then selectively weights the minimum fuzzy input to provide a fuzzy output of the fuzzy logic rule, by multiplying the minimum fuzzy input by a corresponding weight. In one embodiment, a carry bit in a condition code register (60) determines whether the fuzzy logic rule is to be weighted. In response to the single REVW instruction, the data processing system (10) further performs this selective fuzzy rule weighting operation for all rules in a fuzzy rule base.

Abstract: A flexible asymmetrical digital subscriber line (ADSL) transmitter is able to operate simultaneously with integrated services digital network (ISDN) terminal equipment (TE) using a common telephone line (18). The ADSL transmitter changes the frequency content of a frequency-encoded ADSL signal (104) so that its frequency content does not overlap the frequency content of the ISDN TE signal. A corresponding ADSL receiver located within a central office (CO) adapts to the changed frequency content, allowing the ADSL signal to be transmitted over the telephone line without substantial loss of signal integrity. In one embodiment, an ADSL transmitter (100) converts ADSL symbols making up the frequency-encoded ADSL signal (104) into a corresponding time domain signal. The transmitter (100) then interpolates the time domain signal and high pass filters the interpolated signal. This high pass filtered signal is then converted to analog form, bandpass filtered, and driven onto the telephone line (18).

Abstract: A pipelined dual port integrated circuit memory (20) includes an array (30) of static random access memory (SRAM) cells, where each of the memory cells (80) is connected to a single word line (72) and to a single bit line pair (74, 76). A control circuit (32) controls access to the memory cells, where substantially simultaneous requests for access are serviced sequentially within a single cycle of a clock signal of a data processor that is accessing the memory (20). An address collision detector (110) compares addresses provided to the two ports, and generates a match signal that is used for determining which of the two ports are serviced first, independent of which port is read from, or written to. Because dual port functionality is obtained using a single port SRAM array (30), the memory (20) may be manufactured using relatively less integrated circuit surface area, and therefore at a lower cost.

Abstract: A memory (10) such as a current sensing static random access memory (SRAM) achieves fast write recovery through bit line loads and two additional mechanisms. First, an additional load (252) on shared data lines also becomes active to speed the write recovery process. Second, multiple columns (200, 202, 204) are connected to common data lines during write recovery so that a column written to during a write cycle may be again precharged in part by charge sharing using the charge stored in other columns. These two mechanisms allow fast write recovery with minimum column pitch and avoid the problems which would be encountered if the loads were placed on the write data line.