Abstract: A digital signal having a plurality of bits is apportioned by the DAC into a plurality of words, at least one of which has a plurality of bits. Each of the plurality of words is then processed in an energy signal producing means, such as a .SIGMA.-.DELTA. modulator, to produce an output energy signal whose time average represents the input digital word portion. The energy output signals are then summed to provide the analog signal.

Abstract: A logic circuit for receiving both CMOS- and CML-level input voltages in one embodiment performs a logical OR function. A reference bipolar transistor is coupled to a first power supply voltage terminal through a first resistor. A second bipolar transistor for receiving a CML-level input signal is coupled to the first power supply voltage terminal through a second resistor. Emitters of the bipolar transistors are connected together. A MOS transistor for receiving a CMOS-level input signal has a drain connected to a collector of the second bipolar transistor, and a voltage dropping portion seperate the source of the MOS transistor from the emitters of the reference transistor and the bipolar transistor. The input voltages control a constant current conducted from a current source connected to the source of the MOS transistor. The logic circuit base-to-emitter reverse bias caused by CMOS logic levels.

Abstract: A self-adjusting precharge level circuit for coupling to an N-channel precharged bus line. The precharge circuit comprises first, second, and third N-channel transistors and first and second inverters. The first transistor couples the bus line to a positive power supply voltage terminal during a precharge period when the voltage on the bus line falls below the positive power supply voltage minus an N-channel MOS transistor threshold. The second and third transistors together couple the bus line to a second power supply voltage terminal during the precharge period when the voltage level of the bus line rises above positive power supply voltage minus the N-channel MOS therehold, after the voltage level is sensed by the first and second inverters. Sensing and adjusting the voltage in this manner allows the circuit to maintain an N-channel precharge level on a bus which has circuits driving CMOS levels coupled to it, while dampening the voltage response and suppressing oscillation.

Abstract: A variable length shifter for performing multiple shift and select functions. The shifter has a number of cells equal to an operand length, ordered from a most significant to a least significant, or leftmost to rightmost. Each cell stores a bit of the operand, and is coupled to each adjacent cell and to a cell four bits adjacent in either direction, if any. In addition, each cell is coupled to a return bus for implementation of boundary conditions associated with the operation. Besides being expandable to an arbitrary size operand, the shifter implements a register select function using primarily existing circuitry.

Abstract: An output driver circuit with improved output stage clamping comprises an input stage, an output stage, and a clamping circuit. The input stage amplifies a difference between an input signal and a reference signal to provide first and second output signals for driving gates of first and second transistors which together form the output stage. The first and second transistors are serially coupled between first and second power supply voltage terminals and provide an output signal. The clamping circuit clamps the first signal at a predetermined gate-to-source voltage below the first power supply voltage, and clamps the second signal at a predetermined gate-to-source voltage above the second power supply voltage terminal. The clamp voltages are maintained by matching current densities and bias conditions between the first and second transistors, and corresponding transistors in the clamping circuit.

Abstract: A synthesizer is placed in standby mode when a standby portion of a control register is set. Once standby is activated, any detectors and counters are inhibited. The inputs and outputs are reconfigured so as to minimize current drain and to stabilize the VCO control voltage. Recovery from standby is accomplished in two phases. The first phase is started by the receipt of a terminate standby signal. This enables the inputs and starts the counters. The second phase is activated when a signal is received from a feedback counter indicating it has completed a cycle. This causes the preset data to be loaded into the reference counter. The counters are then synchronized; the detector is initialized; and the detector output is enabled. The device also controls an output lock detector and reference frequency signal during the standby mode. The system is also compatible with variable modulus prescalers.

Abstract: An absolute value decoder for decoding an absolute value of an input number in two's complement format. The absolute value decoder receives the input number and inverts each bit. Each bit and each inverted bit are provided to a plurality of columns, and each of the plurality of columns predecodes a unique value of the input number. A precoded signal is precharged during a precharge period and subsequently discharged in response to corresponding bits in the input number not matching the unique number corresponding to the predecoded signal. A grouping portion combines sets of two signals corresponding to a negative number and a positive number of a given absolute value, and provides output signals in response. In another embodiment, columns of transistors provide the predecoded signals for ranges of numbers which can be grouped further so that the absolute value decoder functions as a range detector.

Abstract: A digital signal having a plurality of bits is received by a converter. Two of the bits, the most significant bit and a second bit which is not the most significant bit or the second most significant bit, are tapped from the output and used as a feedback signal. These two bits are also used to form an analog output signal. The two bits are attenuated using a weighted network and then summed to provide the analog output signal.

Abstract: A high speed memory with row redundancy has a plurality of memory cells arranged in rows, with additional redundant rows. When a defect is detected in a row, a redundant row is used in place of the defective row. Each row select signal is decoded by a predecoder, receiving a row address, and a decoder, comprising a NOR gate and an output driver. The NOR gate performs a logical NOR on a set of predecoded signals. The output driver receives the output of the NOR gate and has a bipolar portion and a CMOS portion to provide a row select signal, with a fast rise time and with a CMOS voltage level, to each of a plurality of memory blocks. A defective row is deselected by blowing two fuses which are internal to the NOR gate. The fuses are placed adjacent to each other so that the two fuses may be blown in a single operation.

Abstract: A single-ended input to differential output amplifier performs a predetermined transfer function on an input signal substantially independently of nonlinearities in component values. The input signal and a first reference voltage are coupled to a circuit network, which is coupled to a fully differential operational amplifier, to implement the predetermined transfer function. A common mode voltage between positive and negative output signals of the operational amplifier is sensed and fed back to the operational amplifier so that the operational amplifier may set the common mode voltage to a second reference voltage. The circuit network has first, second, and third capacitors, the third capacitor coupled between a positive input terminal and the first reference voltage.

Abstract: A high speed logic circuit with reduced quiescent current receives a plurality of input signals and performs a predetermined logic operation on the plurality of input signals. The predetermined logic operation may be, for example, a comparison of true and complement input signals, or a logical AND of two input signals. In response to the predetermined logic operation, first and second bipolar transistors coupled between first and second power supply voltage terminals are alternately made conductive to provide an output signal therebetween at ECL levels. A biasing portion ensures a proper voltage on a base of the second bipolar transistor. A current portion draws current from the base of the second bipolar transistor until the voltage of the output signal reaches a logic low voltage, and then makes the second transistor nonconductive, keeping the quiescent current of the circuit to a minimum.

Abstract: An integrated circuit with reduced size through improved power supply distribution. A bonding pad supplies V.sub.SS to an integrated circuit memory, which is distributed through a plurality of power supply lines in a first metal layer and a plurality of grid lines in a second metal layer intersecting at right angles. The plurality of grid lines are placed in unused spaced in the second metal layer and are coupled to the power supply lines in the first metal layer. Together the grid lines and the power supply lines provide an improved power supply by lowering the impedance from a point on the integrated circuit to V.sub.SS supplied on the bonding pad. While this technique is ideally suited to memory devices because of the repetitive nature of blocks of memory cells, other types of integrated circuits can also utilize such a power supply distribution technique.

Abstract: A sense amplifier with an integral logic function for use in a circuit such as a tag cache portion of a microprocessor cache. In one form, the integral logic function is an exclusive-OR function. The sense amplifier senses a differential voltage developed between a differential pair of bit lines which are coupled to predetermined bit positions of a plurality of entries in a tag cache. While sensing the voltage, an exclusive-OR function is performed between the logic state of the sensed bit and a corresponding input address bit. If the input address bit matches the sensed bit, then a match signal is asserted. The value of the corresponding input address bit configures the circuit either to provide an output signal in a predetermined logic state if a true bit line signal voltage exceeds a complement bit line signal voltage, or to provide the output signal in the predetermined state if the complement bit line signal voltage exceeds the true bit line signal voltage.

Abstract: An input/output circuit of an integrated circuit with a programmable input sensing time. The output driver of the input/output circuit is open drain and is designed for use in a wire-OR configuration with other devices. The input/output circuit is coupled to a bonding pad and through the bonding pad to a device pin, and counts a programmable number of clock cycles between a negation of an output drive signal and when the state of the pin is sampled as an input. Since different applications use a wide range of values for external pullup resistors, the input/output circuit allows adjustment of the sample time to fit a particular application.

Abstract: An operational transconductance amplifier (OTA) with improved linearity and improved dynamic range operating on a single five-volt supply. The OTA comprises a virtual ground circuit, a current diverting portion for diverting current through first and second paths to the virtual ground circuit substantially proportional to a differential input voltage, a resistive portion, a current mirror for mirroring currents in the first and second paths into third and fourth paths, respectively, and output stage biasing for providing differential output currents. The resistive portion comprises first and second saturated MOS transistors, the voltage-current characteristics of the MOS transistors making them operate as large-valued resistors because of the short channel effect. The saturated MOS transistors improve linearity and dynamic range by decreasing the variation in output current caused by fluctuations in input voltage. In one form, the current mirror portion is implemented using PNP bipolar transistors.

Abstract: An integrated circuit memory with improved di/dt control. The memory stores a plurality of data bits at intersections of word lines and bit line pairs. In response to a change in at least one of a plurality of address signals during a read cycle, first and second precharge signals are asserted, the second precharge signal asserted after the first precharge signal. An output buffer provides a data output signal at a voltage between a logic high and a logic low voltage in response to an assertion of the second precharge signal, and provides said data output signal corresponding to a voltage on an enabled bit line pair in response to a negation of the first precharge signal. Thus, the voltage on the data output signal changes less when the data bit is provided during the data period. The memory thus improves di/dt for a given access time, or conversely, allows reduced access time for a given di/dt.

Abstract: A memory which senses output signals from a selected memory cell during a read cycle using a non-address transition detection apparatus. The memory has a plurality of memory cells which provide signals to a pair of bit lines when selected. An input circuit drives word lines and select a bit line pair of a memory cell located at the intersection of a selected word line and a selected bit line pair. The memory cell outputs bit line signals which are sensed by a combination of a differential amplifier, a level shifter, and a transconductance amplifier, and are thereafter output and presented externally at a logic state representative of a differential current at outputs of the transconductance amplifier. The combination sensing apparatus and a method for constructing such an apparatus decrease access time significantly over a prior art memory using address transition detection.

Abstract: An output buffer in an integrated circuit comprising voltage regulator, a predriver, and an output stage. The integrated circuit comprises a chip and a package and interconnections therebetween. The voltage regulator is coupled to a first power supply voltage terminal and a second power supply voltage terminal, and provides a regulated voltage signal characterized as having a constant voltage substantially independent of fluctuations in voltage between the first power supply voltage terminal and the second power supply voltage terminal. The predriver receives the regulated voltage signal and a data input signal and provides a regulated predriven signal in response to the data signal. The output stage receives the regulated predriven signal and provides an output signal in response thereto. The output signal is driven onto a bonding pad of the device to provide an interconnection point between the chip and the package.

Abstract: A phase locked loop for providing a programmable frequency output signal with reduced phase-frequency lock time. A phase detector detects a phase difference between a reference frequency divided by a first number, and a frequency of the output signal divided by a second number. First and second counters receive the first and the second input numbers to divide a respective frequency. Whenever an input number is loaded, a load signal resets the phase detector and causes each counter to be loaded, which reduces the lock time of the loop.

Abstract: A stable digitally controlled driver circuit having an output stage with two series-coupled transistors of opposite conductivity type. The driver circuit operates as an analog amplifier with a digitally controlled output stage. The digital control is provided by control transistors which selectively alternately couple a gate of each transistor in the output stage to the output of a differential amplifier. An output signal of the driver circuit is fed back to the input of the differential amplifier to provide a voltage gain determined by the feedback configuration. When both of the series-coupled transistors in the output stage are made nonconductive, the driver circuit's output is in a high impedance state thereby providing a three-state output.