Abstract: A phase locked loop (20) includes a standby control circuit (30) and recovers from standby with minimum lock time. A reference counter (21), a loop counter portion (22, 23) and a phase detector (24) are disabled in response to an activation of a standby signal. Both the reference counter (21) and the loop counter portion (22, 23) are enabled in response to a deactivation of the standby signal. A voltage controlled oscillator (VCO) (26) output signal is decoupled from an input of the loop counter portion (22, 23) in response to an activation of a loop counter output signal. The VCO output signal is next recoupled to the input of the loop counter portion (22, 23) in response to an activation of a reference counter output signal. Finally, the phase detector (24) is enabled. In one embodiment, the loop counter portion (22, 23) includes a prescaler (22) which does not have a separate reset input, and a separate loop counter (23).

Abstract: A flexible data interface (21, 22) for a digital-to-analog converter (25, 26) includes a mute circuit (46, 70, 71 ) to mute and de-mute input data in 6 dB steps over a time period such as one-quarter of a second. The mute circuit includes a counter (46) to provide mute signals, a decoder (70) to decode the mute signals, and a shift matrix (71) to shift the data from zero to the maximum number of bits in response to the decoded signals. The interface (21, 22) includes a programmable shift register (43) to allow different data word lengths, such as 20-, 18-, or 16-bit, to be presented to the digital-to-analog converter (25, 26). The interface (21, 22) also includes a multiplexer (47) to allow left- and right-channel data to be received either time-multiplexed on a single pin, or on two separate pins.

Abstract: A multi-bit sigma-delta analog-to-digital converter (ADC) (40) includes a sigma-delta modulator (41) with a multi-bit quantizer (46) and a digital-to-analog converter (DAC) (47). An output of the DAC (47) provides an error signal of the modulator (41). The quantizer (46) provides a quantized signal having multiple bits ordered from a most-significant bit, to a second most significant bit, to at least one lower-order bit including a least-significant bit. At least two of these bits, including the most significant bit and one of the lower-order bit or bits, are provided as inputs to the DAC (47). The remaining bits are provided as inputs to a prefilter (49), which performs the same transfer function as a comparable multi-bit modulator. A summing device (49) subtracts the output of the prefilter (48) from the quantized signal. A decimation filter (50) resamples the output of the summing device (49) to provide the output of the ADC (40).

Abstract: A digital integrator (22) reduces circuit area and power consumption by implementing a two-stage integration for a decimator with only one adder (51). In the z-domain, he transfer function of a two-stage integrator can be expressed as H(z)=(1/(1-z.sup.-1)).sup.2. Expanded, the transfer function is expressed as H(z)=(1/(1 -2z.sup.-1 +z.sup.-2)). The inverse z-transform yields the expression y[n]=x[n]+2y[n-1]-y[n-2], which can be implemented with a single adder (51) and two delay portions (52, 55 and 53, 54). In one embodiment, a three-stage integrator (22) can further be implemented within a single adder circuit (91) by time-multiplexing an addition required for the two-stage integration with an addition required for a one-stage integration inside the adder circuit (91).

Abstract: A sigma-delta digital-to-analog converter (DAC) (40) receives oversampled input data representative of an analog signal. The data may be optionally interpolated to a higher rate in a interpolator (41). A noise-shaping sigma-delta modulator (42) is connected to the output of the interpolator (41). The output of the modulator (42) is provided to a finite impulse response (FIR) filter (43). The FIR filter (43) has a frequency response characteristic which reduces the shaped noise and aliased components. This noise has a tendency to intermodulate back into the DAC's passband. The FIR filter (43) uses a series of flip-flops (81, 82, 83) functioning as delay elements with well-controlled timing edges. The outputs of the flip-flops (81, 82, 83) control current sources (91, 92, 93) weighted according to corresponding filter coefficients. The outputs of the current sources (91, 92, 93) are then summed in a summing device such as an amplifier (101).

Abstract: A signal processor such as an ADPCM decoder (28b) receives an input signal. As part of the CCITT Recommendation G.726 algorithm, ADPCM decoder (28b) processes the input signal to provide a linear reconstructed signal s.sub.r (k). When enabled, a noise detector (50) samples the reconstructed signal s.sub.r (k) once for each of a predetermined number of received samples. The noise detector (50) adds the absolute value of the reconstructed signal s.sub.r (k) to a total energy estimate. At the end of the predetermined number of samples, the noise detector (50) compares the total energy estimate to a product of a noise threshold and the predetermined number. If the total energy estimate exceeds this product, then a noise indication is provided. This calculation prevents the need for time-consuming division operation which is difficult for high-performance digital signal processors (70).

Abstract: A signal processor such as an ADPCM decoder (128b) receives an input signal. As part of the CCITT Recommendation G.726 algorithm, an inverse adaptive quantizer (41) processes the input signal to provide a quantized difference signal d.sub.q (k). When enabled, a noise detector (50) samples signal d.sub.q (k) once for each of a predetermined number of received samples. The noise detector (50) adds the absolute value of signal d.sub.q (k) to a total energy estimate. At the end of the predetermined number of samples, the noise detector (50) compares the total energy estimate to a product of a noise threshold and the predetermined number. If the total energy estimate exceeds this product, then a noise indication is provided. In another embodiment (228b) a noise detector (250) compares an existing energy estimate signal d.sub.ml (k) computed by an adaptation speed control block (48) as part of the G.726 algorithm to an energy threshold to save processing time.

Abstract: In an asynchronous communication system such as a V.32 modern (80), an input signal is sampled at a near-end clock rate. Each sample is then interpolated in an interpolation filter (92) to provide corresponding interpolated values. The interpolation filter (92) uses a selected one of a predetermined number of sets of windowed sinc function coefficients, each set having a successively greater phase offset. A time drift between near-end and far-end clocks is measured by tracking the coefficient shift in a passband phase-splitting, fractionally-spaced equalizer (95). When the time drift exceeds a threshold, a subsequent set of windowed sinc function coefficients is selected. When the time drift exceeds the threshold after the last set of coefficients is used, the first set is again selected and an interpolated value is either dropped or repeated in forming the far-end data samples.

Abstract: A modified Widlar current source (74) includes a first transistor (84) having a collector providing a first terminal of the current source (74), a base, and an emitter connected through a first resistor (85) to a second terminal of the current source (74). A second transistor (82) has a collector connected to a power supply voltage terminal through a second resistor (81) and to the base of the first transistor (84), a base connected to the collector thereof, and an emitter connected to the second terminal of the current source (74) through a third resistor (83). A switching portion (80) selectively reduces a resistance between the power supply voltage terminal and the collector of the second transistor (82) in response to a control signal. Thus, current is selectively reduced, such as during a non-switching time of a logic circuit (70).

Abstract: A memory (30) includes input buffers (35, 38, 56), decoders (31, 32, 36), and a memory portion (34). The input buffers (35, 38, 56) include a delay circuit (82) which delays at least one transition of an input signal. The delay circuit (82) includes a compensation circuit (250) which compensates the delay circuit (82) for voltage, temperature, and processing variations. In one embodiment, the delay circuit (82) includes a CMOS inverter (102, 103) with an additional transistor (101) coupled between a source of an inverter transistor (102) and a corresponding power supply voltage. The compensation circuit (250) provides a bias voltage to bias a gate of the transistor (101) to determine the delay of the delay circuit (82). The compensation circuit (250) provides the bias voltage as that voltage which biases the transistor (101) to conduct a precision reference current.

Abstract: A data processor (10) having an instruction fetch unit (12), a decode and control unit (14), and an execution unit 16 performs conditionally executed instructions in hardware. A conditional break instruction, BRKcc, is inserted within a looping instruction to conditionally terminate the looping instruction with a minimum number of instruction cycles. A conditional do-loop instruction, DO#0, prevents the data processor (10) from executing a do-loop with a loop count within a loop counter (24) of zero upon entry. A conditional repeat instruction, REP#0, prevents a repeat instruction from being executed if a loop count is zero upon entry. A conditional repeat instruction, REPcc, allows a subsequent instruction to be conditionally terminated during execution.

Abstract: A driver circuit (33) for output buffers or the like provides differing switching speed and di/dt depending on whether an output signal is switched in response to input signals or a control signal.

Abstract: A voltage limiter (20) includes a resistor (21) receiving an input signal on a first terminal and providing an output signal on a second terminal, and a capacitor (22) connected between the second terminal of the resistor (21) and ground. Two transistors (23,26) biased by first and second bias voltages, respectively, are connected between the second terminal of the resistor and a second voltage terminal to clamp the output voltage between high and low voltage limits. A single-ended to differential converter (60) uses two such voltage limiters. A first voltage limiter (90) receives an input voltage, and has an output terminal connected to a positive input terminal of an amplifier (100). A second voltage limiter (92) has an input terminal connected to the second voltage terminal and an output terminal connected to a negative input terminal of the amplifier (100). A shared capacitor (83) is coupled between second terminals of resistors of the first (90) and second (92) voltage limiters.

Abstract: A high-speed magnitude comparator circuit (30) receives two n-bit operands and provides first and second signals for each bit position. The first signal is a logical OR of a complement of a corresponding bit from the first operand and a corresponding bit from the second operand; the second signal is a logical AND of a complement of the corresponding bit from the first operand and the corresponding bit from the second operand. The second signal corresponding to the least-significant bit position is formed differently, as the logical OR of a complement of the least-significant bit of the first operand and the least-significant bit of the second operand. These signals are then provided to pullup (34) and pulldown (35) columns of transistors to determine the results of the comparison in parallel. Thus, the operands need only propagate through three logic levels to provide the result.

Abstract: A data processing system (10) has programmable normal and low voltage modes of operation. The normal voltage mode of operation enables precharge transistors (32, 34) to couple a voltage of (V.sub.DD -V.sub.tn) to each of a plurality of precharge circuit nodes, such as precharge bus (30), within data processing system (10). During the low voltage mode of operation, the full V.sub.DD is coupled to each precharge circuit node, wherein the power supply voltage during the low voltage mode of operation is reduced. Data processing system (10) has a voltage mode bit (36) for receiving voltage mode information from a source external to data processing system (10). In response to an active logic state within voltage mode bit (36), a low voltage mode clocking circuit (42) is enabled.

Abstract: An integral digital receive gain (44) for a G.721 or G.726 ADPCM decoder (28a) or the like in an application such as a CT-2 handset (20) allows digital volume control without the need for external components. The digital receive gain (44) receives a reconstructed signal s.sub.r (k) and a variable gain factor. The integral digital receive gain (44) multiplies the reconstructed signal by the gain factor and provides the result as an input to an output PCM format conversion (45). The digital receive gain (44) also disables a synchronous coding adjustment (46) if a gain setting other than unity gain is detected.

Abstract: A bandgap voltage reference circuit (50, 100) which operates at low power supply voltages provides a reference current as either a one- or a two-.DELTA.V.sub.BE voltage across a first resistor (82, 133). A current proportional to the reference current is mirrored into one terminal of a second resistor (94, 133) to provide the bandgap voltage. Compensation for base currents injected into the circuit (50, 100) by two transistors forming the .DELTA.V.sub.BE reference is provided. In one embodiment (50), base currents of first (66) and second (87) transistors which have equal emitter areas and collector current density as the two transistors (68, 85) forming the .DELTA.V.sub.BE reference compensate for the injected base currents. In another embodiment (100), a single transistor (127) injects current substantially equal to the sum of the base currents of the two transistors (116, 121) forming the .DELTA.V.sub.BE reference.

Abstract: An apparatus for performing multiplications with reduced power includes an arithmetic logic unit and a decode block for performing an equivalent of a multiply instruction. A frequently-encountered multiply instruction occurs between a variable and a known constant. If the known constant is positive or negative one, the decode block enables the arithmetic logic unit to either add the variable to zero, or subtract the variable from zero, in response to the sign bit of the known constant. In response to a multiply and accumulate instruction between a variable and a known constant of positive or negative one, the decode block enables the arithmetic logic unit to either add the variable to the prior accumulated result or to subtract it therefrom, in response to the sign bit of the known constant. In either case, the high-speed multiplier is disabled and its power saved.

Abstract: A dynamic random access memory includes memory cells located at intersections of word lines and differential bit line pairs. A row decoder activates a word line in response to a row address. A first sense amplifier coupled to each bit line pair then increases the small differential voltage of the bit line pair to positive and negative power supply voltages. The first sense amplifier is then isolated from the bit lines so that the bit lines may be equalized. The contents of memory cells along the activated word line are stored in corresponding first sense amplifiers, and the memory functions as a by-one static random access memory during successive page-mode cycles. At the end of the page-mode cycles, the first sense amplifiers are recoupled to the bit lines, and second sense amplifiers update modified data and refresh the charge stored in the memory cells.

Abstract: A digital-to-analog converter (20) includes a linear interpolator (24) and a converter (25, 26) such as a sigma-delta modulator (25) and an associated analog summing network (26). The linear interpolator (24) includes a differentiator (200), an integrator (202), and a multiplexer (201). The differentiator (200) differentiates a received signal at a first rate. The multiplexer (201) multiplexes an output of the differentiator (200) to provide a multiplexed signal having a larger number of bits than the received signal in order to support multiple interpolating ratios. The integrator (202) integrates the multiplexed signal at a second rate to present to the converter (25, 26). By connecting the multiplexer (201) between the differentiator (200) and the integrator (202), the digital-to-analog converter (20) minimizes the size of the linear interpolator (24) while relieving a critical path between the linear interpolator (24) and the converter (25, 26).