Abstract: A television tuning system includes control apparatus for changing the frequency of a local oscillator signal during a search and a comparator arrangement for determining when an AFT signal traverses first and second threshold values corresponding to first and second frequencies in respective "hump" regions of the AFT signal. The frequency of the local oscillator is set to the average of the first and second frequencies in order to set the frequency of the IF picture carrier closer to the nominal value than the first and second frequencies.

Abstract: A component audio/video system includes a system controller having an input/output port adapted for connection via a bidirectional data bus to a plurality of peripheral audio/video devices. At times determined by a system master clock the controller transmits, via the bidirectional bus, user programmed sequences of commands at user specified times to user selected peripheral devices for controlling the operating modes thereof. After transmission of a command of a sequence, the controller monitors the bus to detect a received return status message from the selected device and in response to the received message selectively (1) re-transmits the last command, (2) interrupts the transmission and (3) transmits a further command in the sequence whereby a number of individual devices may be controlled by a single master clock and the possiblility of conflict between a currently transmitted command and a current device operating mode is minimized.

Abstract: An NTSC compatible, single channel widescreen EDTV system encodes and decodes a television signal comprising (1) a main, standard format NTSC signal wth auxiliary low frequency side panel image information compressed into an overscan region thereof; (2) auxiliary high frequency side panel image information; and (3) auxiliary high frequency horizontal luminance information. High frequency components 2 and 3 are subjected to non-linear amplitude companding, with large amplitude compression at an encoder and inverse amplitude expansion at a decoder.

Abstract: An NTSC compatible, single broadcast channel, widescreen EDTV system encodes and decodes a television signal comprising: (1) a main, standard formal NTSC signal component with low frequency side panel image information compressed into the overscan regions thereof; (2) a time expanded high frequency side panel image information component; and (3) an extended high frequency horizontal luminance image information component. Components (2) and (3) quadrature modulate an alternate subcarrier, other than a chrominance subcarrier, having an alternating phase unlike that of the chrominance subcarrier.

Abstract: A unitary tuning structure of a UHF tuner includes an inductance loop, an inductance adjustment element attached to a top portion of the inductance loop so as to be foldable with respect to the inductance loop about an axis parallel to the printed circuit board to which the inductance loop is attached and a capacitance adjustment tab attached to a side portion of the inductance loop so as to be foldable with respect to the inductance loop about an axis perpendicular to the printed circuit board. In another form of the unitary tuning structure, a second inductance loop can be attached within the first loop.

Abstract: A picture-in-picture video signal generator includes a source of an auxiliary video signal, and a producer of successive samples representing the auxiliary video signals. A self-sequencing memory includes a data input terminal coupled to the producer of auxiliary video samples; a write address input terminal, for receiving an initial write address; a data output terminal and a read address input terminal for receiving an initial read address. Write control circuitry is coupled to the write address terminal of the self-sequencing memory, and generates initial write addresses in synchronism with horizontal line intervals of the auxiliary video signal. A source of a main video signal is also provided. Read control circuitry is coupled to the read address terminal of the self-sequencing memory, and generates initial read addresses in synchronism with horizontal line intervals of the main video signal.

Abstract: A power supply includes a source of first and second switching signals that are at opposite phases. First and second MOS power transistors have main current conducting electrodes coupled to a transformer and have gate electrodes that are respectively coupled to the first and second signals to provide push-pull operation. When a transition occurs in a first one of the MOS transistors from a conductive state to a nonconductive state, a voltage is developed at its gate electrode due to its input Miller capacitance. The gate electrode voltage is coupled to a control terminal of a controllable attenuator that attenuates the switching signal that is coupled to the gate of the other MOS transistor. This delays the initiation of the conductive state in the other MOS transistor until immediately after the first transistor becomes nonconductive, thereby avoiding simultaneous conduction in the two transistors.

Abstract: A video memory system which uses dynamic digital data storage elements allows random access to blocks of 32 pixel values. The pixel values to be stored in a block are applied sequentially to the memory system and the pixel values provided by the memory system are provided sequentially. The block oriented random access memory which stores and provides the blocks of 32 pixel values is configured to be able to perform a block read, a block write and a refresh operation in the time required to provide one 32 pixel block to or from the video memory system.

Abstract: A deflection yoke field modifying device corrects N-S pincushion distortion without increasing A-zone convergence errors. The device may be of the form of a ferrite ring which is located near the electron beam exit end of the deflection yoke. The ring may be mounted on the yoke insulator. The ring shunts flux from the vertical deflection field in order to provide the desired N-S pincushion correction.

Abstract: A dual port digital memory system, which includes integral memory sequencing circuitry, is controlled by a bit-serial address and control signal. The address and control signal, which includes a data read address, a data write address and a control value, is serially loaded into a shift register. The address sequencing circuitry loads the read and write address values into integral read and write address registers and, based on the control value, initiates respective read and/or write operations.

Abstract: A receiver includes a video switch operated by a controller for selecting antenna or auxiliary (baseband) video signals for display. When placed in a "VCR" operating mode the controller first selects the auxiliary input for display. If a video signal is not present at the auxiliary input the controller causes the switch to select the output of a tuner thereby providing an automatic signal search to locate the VCR signal which may be applied to either of the antenna and auxiliary inputs. An extension of the search includes tuning the tuner to channel 3 and, if no signal is found, tuning the tuner to channel 4. Upon failure to find an active video signal on either channel the tuner is returned to the last channel received prior to selecting the VCR mode of operation thereby releaving the user of both mode selection and channel selection requirements for locating the VCR signal.

Abstract: A charge pump arrangement receives a digital error word representing an error signal and charges or discharges a capacitor in accordance with the sign of the error word by an amount that is proportional to the absolute value of the error word. The voltage produced in the capacitor is coupled to a frequency control terminal of a voltage controlled crystal oscillator that is used in, for example, a stereo decoder.

Abstract: A processor for expanding a compressed video signal includes a pixel interpolator which interpolates between input pixel values in two dimensions. This interpolator calculates and stores intermediate pixel values which are interpolated in the vertical direction. A pair of these intermediate pixel values are then fed back into the interpolator which performs a horizontal interpolation to produce pixel values that are interpolated in both the horizontal and vertical dimensions. In steady state operation, the horizontal and vertical interpolation operations are alternated to produce a stream of two-dimensionally interpolated values.

Abstract: Circuitry for aligning the transition of a clock signal to transitions of a horizontal line synchronizing signal includes a series of delay elements which provide a plurality of clock signal phases. The longest phase delay provided by this circuitry is greater than the period of the clock signal. The clock signal and the delayed clock signal phases are applied to circuitry which selects one clock signal phase, which has a transition occurring within a predetermined time interval of the transition in the horizontal line synchronizing signal. Other circuitry, coupled to this selection circuitry, inhibits the selection of any clock phase having a greater time delay than the selected phase. This prevents the selection of multiple clock phase signals.

Abstract: In a TV receiver having a zoom system, the chroma signal is vertically and horizontally expanded by repeating the successive lines and pixels. The polarity of the vertically and horizontally chroma signal is selectively inverted in a manner restoring the phase coherence in the output signal.

Abstract: A switch regulator includes a controllable SCR switch that is coupled in series with a filter inductor and a horizontal deflection generator, and the series combination is coupled across a source of unregulated direct voltage for providing a path for an increasing current flow in the inductor during a portion of a trace interval in which the switch is closed. Horizontal rate signals are coupled from the deflection generator to the switch via a first winding for controlling the opening of the switch. A catch diode is coupled to the filter inductor to form a path for a decreasing current flow in the first inductor during at least a portion of a retrace interval. The first winding is coupled in series with a second inductor to form an arrangement that is coupled between the unregulated voltage and the SCR switch. A current in the second inductor maintains the switch conductive during a portion of retrace that varies in accordance with a beam current for improving regulation of an ultor voltage.

Abstract: A deflection circuit output stage generates in a deflection flyback resonant circuit a first flyback voltage at a horizontal frequency. A switch generates in a second flyback resonant circuit a second flyback voltage at the horizontal frequency having a phase relative to that of the first flyback voltage that is controllable. The first and second flyback voltages are summed and applied to a voltage tripler that produces an ultor voltage. A control circuit varies the phase of the second flyback voltage in a negative feedback manner that stabilizes the ultor voltage over a wide range of beam current variations.

Abstract: A picture-in-picture video signal generator includes a source of an auxiliary video signal, and a producer of successive samples representing the auxiliary video signal. A self-sequencing memory includes a data input terminal coupled to the producer of auxiliary video samples; a write address input terminal, for receiving an initial write address; a data output terminal and a read address input terminal for receiving an initial read address. Write control circuitry is coupled to the write address terminal of the self-sequencing memory, and generates initial write addresses in synchronism with horizontal line intervals of the auxiliary video signal. A source of a main video signal is also provided. An interlace inversion detector is coupled to the main and auxiliary video signal sources and produces an inversion detect signal indicating that an interlace inversion condition has been detected.

Abstract: A component audio/video system includes a system controller coupled to supply selection and control commands to a plurality of peripheral audio/video devices and to receive status messages therefrom. The devices may be selected to form a number of different recording configurations involving combinations of one or more recording signal sources and one or more devices for recording the signals. The system controller enters one of a number of different control modes for turning power off to the signal sources and recording devices depending on the status messages identifying recording configurations to enable continued recording by some devices when others run out of recording or playback media.

Abstract: In a television apparatus, a line comb filtered first chrominance signal that is delayed by one horizontal interval and the line comb filtered first chrominance signal that is undelayed are formed from a baseband video input signal. A line comb filtered first luminance signal is also formed from the input signal. A signal that is representative of a difference between the chrominance signals is correlated with a high frequency signal component of the first luminance signal to form a control signal that controls a switching arrangement. The switching arrangement provides combed luminance and combed chrominance signals that are to be displayed in a video display. When the control signal is indicative of the corresponding signals being correlative, the switching arrangement provides, instead, corresponding uncombed signals so as to reduce the visibility of hanging dot condition.