Abstract: A sampled data tone control circuit is implemented using a two pole canonic recursive/non-recursive filter. The filter is programmed with predetermined sets of sample weighting coefficients to selectively cut or boost either the base or treble band of frequencies.

Abstract: A programmable remote control transmitter receives, in a learning mode, remote control codes for remote-controlling various devices and remote-controls the devices according to the received remote control codes by emulating their respective transmitters. The transmitter includes a first repetition pattern discriminator for compressing the remote control codes into first compressed data representing the pulse burst component and the pulse off component a second repetition pattern discriminator for converting pairs of the first compressed data into second compressed data, and a memory for storing the second compressed data. The transmitter also includes circuitry for use in a remote control mode of operation for reconverting the stored compressed data back into codes suitable for transmission to a particular device to be controlled.

Abstract: A Y/C selector switch is coupled to receive a first pair of internally-separated component signals Y.sub.1, C.sub.1 in addition to a second and a third pair of externally-supplied wideband component signals Y.sub.2, C.sub.2 and Y.sub.3, C.sub.3. The switch selects one of the pairs of input signals for application to its output terminals in response to a control signal. Means are provided for disabling the circuitry employed for generating the internally-separated component signals Y.sub.1, C.sub.1 when the Y/C switch is conditioned to apply a pair of externally-supplied component signals.

Abstract: A phase locked loop system for generating a line-locked clock signal for a television signal processing system includes an analog phase-locked loop nested within a digital phase locked loop. The analog phase-locked loop is synchronized to a reference signal which is derived from the most significant bit of a digital oscillator signal generated by a clocked digital oscillator. To reduce instability in this reference signal, the ratio of the frequency of the clock signal to the frequency of the digital oscillatory signal is chosen to be a noninteger value greater than two. In one embodiment of the invention the stability of the reference signal is further enhanced by adaptively delaying transitions in the reference signal by amounts of time that are inversely proportional to the value of the less significant bits of the samples corresponding to the transitions.

Abstract: In a television receiver, an output signal from a binary rate multiplier (BRM) is used to control the amplitude of a video signal and thereby the contrast of a displayed image. Contrast control in response to ambient lighting conditions is accomplished by means of a light dependent resistor which modifies the output pull-up voltage of the BRM.

Abstract: A phase-lock-loop circuit of a deflection apparatus generates a first signal at the horizontal frequency during normal operation. The first signal is coupled to a phase-control-loop circuit that maintains the deflection current timing in phase with the first signal. A fault protection circuit disables the generation of signal transitions in the first signal when a fault condition occurs. A circuit that detects the presence of transition edges in the first signal prevents the operation of the deflection output stage when the transition edges in the first signal are missing.

Abstract: A controlled crystal oscillator of a stereo decoder of a television receiver using CMOS technology includes first, second and third differential emplifiers that produce corresponding first, second and third pairs of anti-phase output signals. The first and second differential amplifiers have variable gains that vary in opposing manners in accordance with a frequency control signal. The oscillatory signal of a crystal is coupled to corresponding input terminals of the three differential amplifiers such that the phase of the signal that is developed at the input terminal of the third differential amplifier is phase-shifted by approximately 90.degree. relative to those developed at the input terminals of the other two amplifiers. The three pairs of output signals are combined to form a single-ended oscillatory signal that is coupled back to the crystal to complete a regulative feedback path. The frequency of oscillation is determined in accordance with the frequency control signal.

Abstract: The invention relates to a display system using a remote control transmitter handunit having both a "pointing function" capability for moving a cursor displayed on a display screen by changing the angular position of the remote control handunit, and the capability of sending dedicated function data directly to the receiver. Thus, numeric data representing, for example, channel number or time of day, being unsuitable for selection from a menu is directly transmitted along with "pointing function" data transmission.

Abstract: In a video display apparatus having a service mode of operation, a vertical deflection circuit includes a vertical deflection winding coupled to a DC blocking capacitor. An output stage is coupled to the vertical deflection winding at an output terminal. A vertical sawtooth voltage generator is coupled to a driver stage for driving the output stage at a vertical rate in a sawtooth manner to generate a sawtooth deflection current in the deflection winding and for establishing a DC operating voltage level at the output terminal that charges the DC blocking capacitor. The sawtooth generator includes a second capacitor that, during normal operation, is charged in a sawtooth manner via a resistor for developing a sawtooth signal. A service mode switching circuit is coupled to the resistor for asserting the service mode of operation by preventing the charging of the second capacitor via the resistor. A DC feedback loop maintains the DC blocking capacitor charged during the service mode.

Abstract: In a video display apparatus having an on-screen display feature (OSD), a vertical deflection circuit includes a vertical deflection winding coupled to a DC blocking capacitor. A deflection amplifier responsive to a sawtooth signal is coupled to the vertical deflection winding at an output terminal. A vertical sawtooth voltage generator that generates the sawtooth signal is coupled to an input terminal of the amplifier for driving the output stage at a vertical rate in a sawtooth manner to generate a sawtooth deflection current in the deflection winding. The sawtooth generator includes a capacitor that, during normal operation, is charged in a sawtooth manner via a resistor for developing a sawtooth signal. During a transition interval that follows a user initiated channel selection command, the frequency of the sawtooth signal becomes smaller.

Abstract: A ferrite shield component for suppressing high frequency signals in electrical circuits, such as tuners for television receivers, is formed by surrounding an electrical conductor with ferrite material. The shield component is formed in the shape of a leadless chip to permit placement on a circuit board by chip insertion machines. The conductor pattern and ferrite material may be selected to determine particular impedance-frequency characteristics.

Abstract: In a programmed audio amplifier system, the volume setting when the system is turned on is conditionally related to the last volume setting, i.e., immediately before the amplifier was turned off. At turn-on the system remains at the last volume setting as long as it is less than a preset volume setting. However, at turn-on the system exhibits the preset volume setting if the last volume setting exceeds the preset volume setting.

Abstract: A television picture magnification system which provides real-time magnified video images includes a memory system which stores L horizontal line intervals of samples representing one field of the unmagnified video image during a first time interval and which provide K of those L lines of samples during a second time interval offset from the first time interval by less than one field period. The K lines of samples provided by the memory are interpolated by the system to develop L lines of samples which represent one field of the magnified image. The offset delay between the first and second time intervals ensures that any field of the magnified image includes samples from only one field of the unmagnified image.

Abstract: A television receiver includes a phase-locked loop (PLL) which generates a clock signal having a frequency of N times the line frequency and being phase-locked to the horizontal line synchronizing signal. The clock signal produced by this PLL has a frequency which tends to jitter between N+1 and N-1 times the line frequency. To compensate for this jittering in the frequency of the clock signal, phase alignment circuitry is coupled to the PLL to align the phase of the clock signal to the horizontal drive signal produced by the PLL on the occurrence of each horizontal drive pulse. The PLL also includes a delay element which delays the horizontal drive signal applied to the phase comparator of the PLL. This delay element effectively advances the phase of the horizontal drive signal and the line-locked clock signal with respect to the horizontal sync signal to compensate for signal processing delays imparted in the generation of the horizontal drive signal and the clock signal.

Abstract: A system for generating a series of psuedo random numbers so that numbers in the sequence may be randomly accessed. The system includes apparatus for scrambling the bits of a plurality of seed numbers. The pattern of bit scrambling is governed by the control number. The plurality of scrambled seed numbers are exclusive-OR'ed to produce an output number. As long as the seed numbers remain unchanged, a given control number will always produce the same psuedo random number.

Abstract: A dual port video memory system includes a serial-to-parallel converter coupled to the input data port and a parallel-to-serial converter coupled to the output data port. Four-bit pixel values are clocked into the serial-to-parallel converter synchronous with an input clock signal and are provided by the parallel-to-serial converter synchronous with an output clock signal. The input and output clock signals may have different frequencies, but the negative-going edges of each of these clock signals are synchronized to the negative-going edges of a master clock signal.

Abstract: Apparatus for estimating the square of a multi-bit digital sample having a value (A+B) segments the sample into a most significantf bit (MSB) portion having the value A, and a least significant bit (LSB) portion having a value B. The LSB portion is added back to the sample to produce a sample having a value of (A+2B), which sample is applied to the multiplicand input of a multiplier circuit. The MSB portion of the sample is coupled to the multiplier input of the multiplier circuit which produces the product (A.sup.2 +2AB) as an estimate of the square of the sample. Estimating the square in this manner significantly reduces the size of the multiplier circuit.

Abstract: An adaptive luma/chroma separation apparatus is herein disclosed. Means, including delay elements and bandpass filters, are employed to generate a set of three bandpassed signals B.sub.b, M.sub.b and T.sub.b, which are delayed with respect to each other by one horizontal line period. A control signal generating circuit coupled to receive the three bandpassed signals B.sub.b, M.sub.b and T.sub.b develops a control signal K that determines the relative mixing of the signals. A combining circuit, including a soft switch, combines the three bandpassed signals in response to the control signal K to generate a separated chroma signal C.sub.b. The separated chroma signal C.sub.b is subtracted from the (non-bandpassed) main signal M to generate the luma signal Y.

Abstract: A display system for a video apparatus includes a cathode ray tube and a deflection yoke adapted to be adhesively mounted to the cathode ray tube. A flexible sleeve is removably attached to the tube between the yoke and the tube and closely conforms to the tube contour. The yoke is adhesively mounted to the sleeve rather than directly to the tube in order to permit removal and replacement of the deflection yoke without causing damage to the tube.

Abstract: A full motion color digital video signal is compressed, formatted for transmission, recorded on compact disc media and decoded at conventional video frame rates. During compression, regions of a frame are individually analyzed to select optimum fill coding methods specific to each region. Region decoding time estimates are made to optimize compression thresholds. Region descriptive codes conveying the size and locations of the regions are grouped together in a first segment of a data stream. Region fill codes conveying pixel amplitude indications for the regions are grouped together according to fill code type and placed in other segments of the data stream. The data stream segments are individually variable length coded according to their respective statistical distributions and formatted to form data frames.