Abstract: To improve sensitivity by adding pixels, and improve precision of pixel interpolation in an imaging device. An imaging device is provided in which pixels are added along a horizontal direction or a vertical direction to improve sensitivity of an imaging element. An R pixel signal, a G pixel signal, and a B pixel signal in which pixels are added, for example, along the vertical direction are output from a CCD (12). A CFA interpolation unit (24) interpolates the G pixel signal using an adjacent pixel along the horizontal direction. The CFA interpolation unit (24) also interpolates the R pixel signal and the B pixel signal along the horizontal direction using an adjacent pixel along the horizontal direction and interpolates along the vertical direction using correlation of the interpolated G pixel.

Abstract: Network switching systems (10, 110, 210, 310, 410) for use in an Ethernet network are disclosed. Each of the switching systems includes switch devices (20) supporting multiple (e.g., eight) local ports, and one gigabit high-speed port; each of the high-speed ports are full-duplex ports. Each switching system also includes a gigabit switch device (30) having two full-duplex gigabit ports. According to one aspect of the invention, the switches (20, 30) are connected in a ring using their respective gigabit ports, with each of the switches (20, 30) having a Ring ID value. Upon receipt of a message packet at one of its local ports, the switches. (20) attach a pretag with the Ring ID value upon the packet, and begin forwarding the packet around the ring until the destination address is registered with one of the switches (20, 30), or until the packet returns to the original switch (20) which, upon detecting its own Ring ID value, filters or discards the packet.

Abstract: A circuit (100) for protecting sensitive data stored in a storage area (108) includes a one time programmable device such as a fuse element (104) coupled to the input data path (102), and a one time programmable device such as fuse element (112) coupled to the output data path (118). Once sensitive data is loaded into the storage area (108), either one of, or both of the fuses (104, 112) can be activated (blown) in order to prevent access to the data stored in storage area (108). Optionally, a fuse element (130) can also be added to the internal circuit data line (120) that would prevent both internal and external access to the stored data.

Abstract: A digital subscriber line modem (30) capable of operating with multiple transmission line profiles depending on the current transmission line characteristics of a wire line pair (20) includes an interface (212, 292) to the wire line pair (20) and a signal converter (214, 290) with a terminal coupled to the interface. An on/off-hook detector(300) drives an impedance analyzer function (304) that is able to measure transmission line parameters based on the current line characteristics of the wire line pair (20). A control logic block (310) performs the actions required to adapt to a new line conditions of the wire line pair (20) and rapidly adapt to the new on/off hook condition.

Abstract: A cable modem (20) including a demodulator (25) having an improved carrier recovery circuit (35) is disclosed. The cable modem (20) demodulates phase-modulated signals, including phase and amplitude modulated signals such as quadrature amplitude modulation (QAM) information. The carrier recovery circuit (35) includes a phase detection function (40), preferably realized by way of programs executed by a digital signal processor, that generates a derivative signal (g(x″)) based upon a summation of a complex function of a corrected input signal (x″) over some or all of the possible points in the modulation constellation. In one embodiment of the invention, the derivative signal is an exact evaluation, considered over the sum of all points in the constellation; in another embodiment of the invention, only four small magnitude points, at relative quadrature phases, are included in the summation.

Abstract: A signal filter employs digital control signals to selectively establish and adjust analog impedance components of the filter. In the case of a first-order R-C filter, adjustable resistance and reactance assemblies are coupled in series. The resistance assembly has multiple parallel signal paths sharing a common input and output. Each signal path includes a prescribed electrical resistance and a digital switch to selectively enable and disable the resistance. Between the common input and output, the signal paths provide a collective resistance which varies depending upon which switches have been activated. The reactance assembly is similar to the resistance assembly, with capacitors or inductors instead of resistors. A digital controller selectively activates the switches to adjust the assemblies' respective resistance and reactance.

Abstract: A method of configuring a switch-network to implement programmable gain devices such as Programmable Gain Amplifiers (PGAs). The method provides high-accuracy and low-distortion with small area requirements and less sensitivity to process and temperature variations when compared with traditional programmable gain architectures where the gain is determined by a ratio between one or more fixed resistors and one or more programmable resistors.

Abstract: An acoustic reflector (48) is applied over a thin-film piezoelectric resonator (41, 61) which is supported on a semiconductor or semiconductor-compatible substrate (42, 62) of a microelectronic device (40, 60), enabling an encapsulant (49) to be applied over the reflector-covered resonator without acoustically damping the resonator. In one embodiment, alternating high and low acoustic impedance layers (51, 53 . . . 55) of one-quarter wavelength thicknesses constructively reflect the resonating wavelength to make an encapsulant in the form of an inexpensive plastic molding compound appear as a “clamping” surface to a resonator (41) peripherally supported over an opening (43) on a silicon substrate (42). In another embodiment, an encapsulant- and reflector-covered resonator (61) is mechanically supported above a second reflector (68) which eliminates the need for peripheral support, making substrate (68) also appear as a clamping surface.

Abstract: A very fast lock integer N PLL with hybrid digital coarse VCO tuning and VCO temperature drift compensation provides for a fully digital tuning scheme without the need for charge pumps. A PLL synthesizer (300) using such a PLL design provides for very fast lock times by using an open loop step and a closed loop step. The hybrid PLL can achieve coarse tuning within four clock cycles, while minimizing any errors caused by the VCO non-linearity. Temperature tracking and compensation is also provided. A SAR implementation (100) and an interpolation tuning implementation (200) are also described.

Abstract: An integrated circuit device includes a clock generator having a primary input for coupling to a primary reference frequency source, a secondary input for coupling to a secondary reference frequency source, and an output that produces a primary digital transceiver clock signal having a frequency of chiprate (S)(n) in a primary mode, and a secondiary digital transceiver clock signal having a frequency of chiprate in a secondary power saving mode. A chiprate divider connected to the output of the clock generator produces a primary mode enable signal that has a frequency of chiprate when in a primary mode. A long PN generator and a short PN generator each have a clock input that is coupled to the output of the clock generator. A first multiplexer output produces the primary mode enable signal in a primary mode, and the secondary mode enable signal in a secondary mode.

Abstract: A method and apparatus for producing a variable rate precoded signal are presented in which a variable rate encoder receives a rate control signal and a data signal and generates a constellation size signal and data symbols. The data symbols and constellation size signal can be used by a precoder to produce a variable rate precoded signal. The precoder can be a Tomlinson/Harashima-Miyakawa precoder which uses the constellation size signal as part of the quantization process. The system can also be used to generate a variable rate modulation encoded signal. The invention provides the ability to create a variable rate signal which can be precoded and to which error correcting codes can be readily applied.

Abstract: A method for lowering the spurious output of a sample and hold phase detector includes the steps of charging a ramp node (502) to a first voltage level after a sample period (606) has occurred. After the ramp node (502) is charged to the first voltage level, the ramp node is charged to a second voltage level during period (610). By precharging the ramp node (502) during the hold period (614), it reduces any leakage current in the SH switch (514), which minimizes any voltage drift thereby improving the spurious performance of the SH phase detector (500).

Abstract: A method of communicating from a transmitter to a receiver over a communication medium. For the transmitter, the method includes the step of formatting data into a data stream to be communicated across the communications medium. This data stream comprises a plurality of headers (PACK HEADER). Moreover, for each of the plurality of headers, the method performs two steps. First, the method modifies information encoded by the header by performing a bitwise logical operation between selected bits of the header (B) with a predetermined bit pattern (A). Second, the method transmits the plurality of headers on to the communications medium. For the receiver, the method includes the step of receiving the plurality of headers from the communications medium. Additionally, for each of the received headers, the receiver recovers the information encoded by the header.

Abstract: A USB function device (14) for coupling to a USB host (12). The USB function device (14) comprises circuitry (32) for providing a capability to the USB host, where the circuitry for providing a capability comprises an address space (VBUS). The USB function device (14) further comprises a USB interface circuit (30) coupled between the USB host and the circuitry for providing a capability to the USB host. The USB interface circuit (30) comprises a memory area (44, 106) comprising a write endpoint (1062) accessible to the USB host for writing a plurality of bytes to the memory area via the write endpoint. The plurality of bytes comprise data information and protocol information. The write endpoint comprises an endpoint-type other than a control-type endpoint. The USB interface circuit also comprises circuitry for decoding (166) the protocol information and circuitry for communicating the data information to the address space in response to the protocol information.

Abstract: A phase-locked loop (PLL), particularly useful for ADSL frequency locking applications, uses inexpensive external components in combination with versatile logic that can be implemented in a programmable logic device or an application specific integrated circuit. The PLL has the ability to revert to center-frequency operation in the absence of a timing reference and to adapt to a variety of reference frequencies through logic selection.

Abstract: A telecommunications system using DSL modems (36, 38) detects on-hook or off-hook states of a local loop telecommunications line (18). If the local loop (18) is in an off-hook state, the normal data communication rates are used. If the local loop is in an on-hook state, the unused voice band is allocated to either the upstream band and/or downstream band of the DSL modems, in order to increase data communication rates.

Abstract: A programmable gain amplifier (10) has a differential input (12-13), a differential output (16-17), and a plurality of enable inputs (21, 31-34). The amplifier includes a plurality of transconductor sections (26-29), which each have input nodes coupled to the differential input, output nodes coupled to the differential output, and an enable node coupled to a respective enable signal. The transconductor sections have different gains, which are respective powers of two. Each transconductor section includes a transconductor circuit (51, 56) which is coupled in series with at least one current mirror circuit (52-53, 57-58). Each transconductor circuit has a transistor (121) with a class A quiescent current that is proportional to the corresponding gain, the transistor being sized to achieve an optimum current density for its quiescent current.

Abstract: A system (20) for communicating request information from a first circuit (state machine A) operable according to a first clock domain (CLKA) to a second circuit (state machine B) operable according to a second clock domain (CLKB). In the system, the first clock domain differs from the second clock domain. The system comprises a flag circuit (F2) for storing a flag having a changeable state. The flag circuit comprises an input for receiving a toggle control signal (TOGGLE) and the state of the flag changes in response to assertion of the toggle control signal, where the first circuit is operable to assert the toggle signal to communicate the request information to the second circuit. The system further comprises a synchronizing circuit (SCD) having an input coupled to an output of the flag circuit and for receiving the state of the flag. The system further comprises a detection circuit (ED) having an input coupled to an output of the synchronizing circuit.

Abstract: A client-side modem (20) having capability of improved data rate upstream communications via a codec (2) in a central office (CO) to an Internet service provider (ISP) (10) is disclosed. The disclosed modem (20) includes a digital signal processor (DSP) (14) that, for upstream communications, performs a bit mapping function (22) upon the digital data so that the digital words are mapped to slicing levels of analog-to-digital conversion circuitry (A/D) (6) in the central office codec (2); in addition, bit mapping function (22) preferably maps the digital signal into symbols having fewer bits each than the maximum defined by the number of slicing levels of the A/D (6). A pre-equalize filter function (26) applies an approximate inverse channel response filter (as measured during the training process) to the bit mapped digital data, to maximize the transmitted data rage over the dispersive analog subscriber loop (ASL), with consideration for an average transmit power maximum specification.

Abstract: A digital driver circuit with one or more CMOS inverters intended as input stages, whereby for the MOS FETs of the inverters the channel width/length (W/L) ratio increases from stage to stage. The digital driver circuit includes an intermediate stage with two further CMOS inverters, connected between a supply voltage Vcc and ground. The driver circuit also includes an output stage having two MOS FETs with the drain terminals of both the MOS FETs of the output stage connected both to each other and to the output of the circuit, the W/L ratio of both MOS FETs exceeding that of the MOS FETs of the intermediate stage. The switch-over of the two MOS FETs of the output stage, occurring with changes of the digital input signal at the input of the circuit, is offset in time with respect to each other, thereby reducing current peaks.