Abstract: A frequency synthesizer (500) includes a DDFS (502) and a PLL loop (526). The oscillator frequency signal (516) is used to create the DDFS clock signal (514), fCLK that acts as a system clock for the DDFS (502). With the phase/frequency state of the DDFS being adjusted based on a comparison of the DDFS system clock signal (514) with a frequency reference signal (520), fREF. The DDFS system clock signal (514) is further divided by a divider (512) to establish an update clock signal (528), fupdate. The output of the DDFS and the update clock signal (528) are compared by a phase/frequency detector (504). The output signal of the PFD (504) is preferably filtered by a loop filter (506) before using it as a tuning signal (522) for the DCO (508). The principle of bootstraping ensures that the synthesizer (500) is synchronous and every clock is derived from the same source.

Abstract: The present invention includes an improved switching device (400) which operates in a shared media environment. The switching device (400) in accordance with the present invention includes a tag header processing means (402) operable to insert a tag header into frames that enter the switching device (400) without a tag header and CRC processing means (404) operable to calculate a CRC for the frame excluding the tag header for use while the frame is being processed within the switching device (400). The tag header processing means (402) is further operable, when the internal switch processing of the frame is completed and the frame is ready to be transmitted, to determine whether or not the frame should be transmitted without a tag header and removing the tag header if it is not.

Abstract: The present invention is a code preparation system (12) which accepts input code (11) in intermediate code format, our source code format which is first translated into intermediate format, analyzes the intermediate code, then provides optimization information, hints, and/or directions (collectively referred to as “optimization information”) for optimizing execution of the intermediate code by a code interpretive runtime environment, such as a Java Virtual Machine. The code interpretive runtime environment is operable to selectively implement the optimization information received from the code preparation system (12). The optimization information is provided to the code interpretive runtime environment in the form of additional attributes added to a class file (14) generated by the code preparation system (12).

Abstract: A method and system for controlling data latency in a communication network use a pre-selected portion of the data to identify one of at least two latency paths. The data is transported to a network device (500) through physical channel (502). The network device (500) includes at least two latency paths (506,508), each operable to transport the data through to other parts of the device (500) at an associated rate. In a first aspect of the present invention, data sorter (504) extracts a latency path identifier from the incoming data then provides the incoming data to one of the at least two latency paths (506,508) accordingly. In another aspect of the present invention, the data sorter (504) extracts a indicator from the incoming data which characterizes the incoming data, decodes the indicator to determine which of the at least two latency paths (506,508) to selects, then provides the incoming data to the selected one of the at least two latency paths (506,508).

Abstract: A method and apparatus for supporting multiple bit allocations in a multicarrier modulation system arc disclosed. Hence, symbols being transmitted or received can make use of different bit allocations. By supporting the multiple bit allocations, the multicarrier modulation system is able to support bit allocation on a superframe basis. Also disclosed are techniques for selection and alignment of superframe formats to improve system performance. In the case of data transmission systems involving different transmission schemes, different bit allocations can be used to reduce undesired crosstalk interference.

Abstract: Provided is a symmetrical filter that uses a single comparator. In addition to a voltage divider, a current regulator, and a comparator, the filter of the invention provides control logic that turns on or off a pull up switch and/or pull down switch in order to fully charge or fully discharge a capacitor. Accordingly, in one aspect, the invention is a control logic for a symmetrical filter. Furthermore, timing logic is provided to provide for a more rigorous symmetrical filter performance.

Abstract: Disclosed are radio frequency (RF) interference cancellation techniques that effectively estimate RF interference to the data signals being received using a frequency domain model, and then remove the estimated RF interference from the received data signals. Improved techniques for digitally filtering multicarrier modulation samples to reduce sidelobe interference due to the RF interference are also disclosed.

Abstract: A radio frequency receiver includes a mixer (508) for converting a radio frequency signal into an IF signal. The IF signal is then filtered and amplified by a filter (510) and automatic gain control circuit (512). The filtered and amplified IF signal is then received by an analog-to-digital converter (514) in order to convert the signal from an analog signal into a digital signal. The digital signal is then provided to a decimation filter (516) in order to convert the digital signal into a base band signal (520). The ADC (514) and decimation filter (516) both are provided with a sampling frequency signal (518) which is preferably at least four times greater than the IF signal. By using a decimation filter (516) the need for a second down conversion mixer is eliminated, thereby eliminating any associated noise, power consumption and distortion associated with using a second mixer.

Abstract: The present invention is a channel-aided, decision-directed delay-locked loop (CADD-DLL) implemented, in one embodiment of the present invention, for pilot-symbol-aided (PSA) code-division multiple-access (CDMA) communication. In one embodiment of the present invention initial pseudo-noise (PN) code acquisition is accomplished with the aid of a conventional non-coherent PN code acquisition system, and, upon acquiring the initial PN code epoch, PN code tracking is performed using a channel-aided, decision-directed PN code tracking mechanism. The tracking loop in accordance with the present invention includes delay and advance PN correlators. The correlators are followed by data and phase correction as well as amplitude matching devices, the outputs of which are subtracted to form an error signal for code tracking purposes.

Abstract: A circuit (43) generates one or more signals to be delayed by a corresponding time intervals. Tapped delay lines (40) are coupled to the signals, each tapped delay line including a plurality of delay elements (42) and having a plurality of exit points (E) through which said signal may propagate. A test circuit (20) determines a delay associated with a delay element in the circuit and selects one of said exit points of each of said tapped delay lines based on said delay.

Abstract: A pipelined analog-to-digital converter includes a first stage 700 of an analog-to-digital converter having a first resolution. The first stage 700 includes a three capacitor switched capacitor circuit. The analog-to-digital converter further includes one or more subsequent analog-to-digital converter stages 200. The first and subsequent stages 700 and 200 are pipelined together to provide a digital output signal.

Abstract: CMOS semiconductor dynamic logic (300) is disclosed, comprising dynamic logic circuitry (302) and tunneling structure circuitry (328) coupled to the dynamic logic circuitry; where the tunneling structure circuitry is adapted to hold a node (308) voltage stable by compensating leakage current originating from said dynamic logic circuitry.

Abstract: CMOS semiconductor latch and register (500) circuitry is disclosed, comprising a first tunneling structure latch circuit (502); data input circuitry (506), coupled and adapted to pass data to (504) said first tunneling structure latch circuit (502), a second tunneling structure latch circuit (514), data transmission circuitry (516), coupled between said first and second tunneling structure latch circuits, and adapted to transfer data from said first tunneling structure latch circuit to said second tunneling structure latch circuit, and data output circuitry (518), coupled to (512) said second tunneling structure latch circuit (514).

Abstract: A method of fabricating an integrated circuit (10, 51, 61, 71, 81, 91) includes forming on the upper surface (13) of a substrate (12) a part (18) which has thereon a side surface (19). A plurality of sidewalls (22, 27 and 83-84) are then formed in succession, outwardly from the side surface. A plurality of successive implants (21, 26, 31, 73-74, 87-88, 93-94) are introduced into the substrate, where a respective different subset of the sidewalls is present when each implant is created. The formation of sidewalls and implants may be carried out in an alternating manner, followed by removal of the sidewalls. Alternatively, removal of the sidewalls and formation of the implants may be carried out in an alternating manner. The width of each sidewall may be sublithographic, and the cumulative width of all sidewalls may be sublithographic.

Abstract: An integrated circuit (10, 60, 110, 210) is fabricated according to a method which includes the steps of providing a structure (12, 112, 212) having a top surface (13, 113, 213), and forming spaced first and second sections (16-18, 67-69, 72-73, 126-127, 231-232) on the top surface. The first and second sections have side surfaces (21-26, 81-88, 131-134, 241-244) thereon. A respective sidewall (31-36, 91-98, 141-144, 251-254) with a sublithographic thickness is formed on each side surface. Then, a further section (42A-42D, 101A-101D, 152, 268) is formed in the region between the sidewalls on the first and second sections, for example by introducing a selected material between those sidewalls, and by then removing any portion of the selected material which is higher than the upper ends of the sidewalls.

Abstract: Fixed gain amplifiers have particular use in the read channel of hard disk drives. A CMOS fixed gain amplifier 18c having a constant gain over the large dynamic range of hard disk drive applications is provided by incorporating super follower transistors M3 and M4 into the input stage of the fixed gain amplifier. The super follower transistors are folded into the output stage of the amplifier. The differential current through the degeneration resistor RE1 travels through the super follower transistors M3 and M4 and into the current mirrors I5 and I6. Thus the ac differential current goes directly to the cascoded stage, into the load resistors RL1 and RL2, and to the output load.

Abstract: A open circuit detection circuit for a hard disk drive write head, wherein the write head receives write drive signals from a write driver, and wherein the write driver generates a write drive signal in response to write control signals. The circuit includes a pulse width detector, generating a latch control signal in response to the detection of a write control signal having a predetermined duration. The circuit also includes a comparator comparing the write drive signal to a predetermined reference level and generating a comparison output signal indicative of whether the write driver signal is more or less than the predetermined level. A latch is coupled to receive the comparison output signal, the latch being clocked in response to the latch control signals. The latch output provides an indication of an open circuit.

Abstract: A digital differential receiver IC that rejects the inter-symbol interference (ISI) that is imposed upon differential digital signals when long runs of a digital state (0 or 1) are transmitted over long cables. The ISI-rejecting differential receiver IC is implemented in either bipolar technology (n-p-n or p-n-p) or in insulated gate FET technology (p-channel or n-channel). The primary differential pair of transistors is connected to a secondary differential pair of transistors through a filter network so that a high pass “shelf” filter transfer function exists between the differential input signals and the output signals. This transfer function mitigates ISI by reducing the gain for long runs of a digital state (low frequencies) and enhancing the gain for the state transition edges (high frequencies).

Abstract: A circuit (300) employing metal-oxide-semiconductor (MOS) devices is disclosed. The circuit (300) includes a circuit portion (302) that provides a circuit function, and a body voltage adjust portion (304) which alters the body potential of the transistors within the circuit portion (302). By adjusting the body potentials of the circuit portion (300) transistors, the speed at which the circuit portion (300) can perform its function is increased. A decoder circuit embodiment (800) and sense amplifier embodiments (1200, 1300, 1500, 1600, 1700, 1800, 1900 and 2000) are also disclosed.

Abstract: The invention relates to an integrated CMOS circuit for use at high frequencies with active CMOS components (12) and passive components (16, 18, 20). The active CMOS components (12) are formed in a semiconductor substrate (10) which has a specific resistivity in the order of magnitude of k&OHgr;cm. In the semiconductor substrate (10), and under the active CMOS components (12), a buried layer (22) is formed which has a specific resistivity in the order of magnitude of &OHgr;cm. The passive components (16, 18, 20) are formed in or on a layer (14) of insulating material which is arranged on the semiconductor substrate (10). A conducting contact layer (24) is arranged on that surface of the semiconductor substrate (10) which is not facing the layer (14) of insulating material.