Abstract: A system and method for enhancing the utilization of available bandwidth for an uncached device. Data written to the device is done so by striding the available data into multiple data elements of the appropriate size for the uncached device. Data read from the device is retrieved from multiple addresses on the uncached device to avoid unnecessary waits cycles in the processor.

Abstract: An error-correcting partial latch stage includes a first pass gate having an input for receiving a data input signal, an output, and a control node for receiving a control signal, a second pass gate having an input coupled to the output of the first pass gate, an output for providing a data output signal, and a control node for receiving the control signal, an inverter having an input coupled to the output of the first pass gate and an output; and a correcting inverter stage having a first input coupled to the output of the inverter, and second and third inputs for receiving voting signals from adjacent error-correcting latch stages, and an output coupled to the output of the second pass gate. A full latch stage includes three interconnected partial latch stages. The full latch stage has a high degree of immunity from SEU events and from on-chip noise coupling.

Abstract: Data retention of a ferroelectric transistor is extended by intecting holes or electrons into the ferroelectric transistor when power is removed. The ferroelectric FET has a mechanism to trap charge in a buffer dielectric layer or in the ferroelectric layer sandwiched between a top electrode and a silicon substrate. The state of polarization is detected before power is removed from the ferroelectric FET. Charge is injected into the ferroelectric FET to produce a first threshold voltage when a first polarization state is determined before power is removed. Charge is removed from the ferroelectric FET to produce a second threshold voltage when a second polarization state is determined before power is removed. When the ferroelectric FET is powered up again, the state of charge injected is determined. The ferroelectric FET is then polarized to correspond to a first threshold voltage when the charge state corresponding to the first threshold is determined.

Abstract: A printed circuit board (PCB) assembly comprising a PCB having a top circuitry layer and a bottom layer with a hole through the PCB, a component, and a pallet. The printed circuit board manufactured by a method including forming a hole through the top circuitry layer and the bottom layer, attaching the bottom layer to a pallet, placing the component in the hole, and soldering the component to the top circuitry layer and to the pallet.

Abstract: A bandgap reference circuit includes a current-voltage mirror circuit having first, second, third, and fourth nodes, a transistor having a current path coupled between a source of supply voltage and the first node, a current mirror portion having an input coupled to the first node and a control terminal coupled to the fourth node, a serially coupled first resistor and first diode coupled between the output of the current mirror portion and ground, a serially coupled second resistor and second diode coupled between the third node and ground, a third diode coupled between the second node and ground, and a differential amplifier having a first input coupled to the fourth node, a second input coupled to the output of the current mirror portion for generating a bandgap reference voltage, and an output coupled to the gate of the transistor.

Abstract: A method of chemical-mechanical polishing for forming a shallow trench isolation is disclosed. A substrate having a number of active regions, including a number of relatively large active regions and a number of relative small active regions, is provided. The method comprises the following steps. A silicon nitride layer on the substrate is formed. A number of shallow trenches are formed between the active regions one or more of which may constitute an alignment mark. An oxide layer is formed over the substrate, so that the shallow trenches are filled with the oxide layer. A partial reverse active mask is formed on the oxide layer. The partial reverse active mask exposes a portion of the oxide layer over the large active area and over the alignment mark. The oxide layer of each large active region and the alignment mark is removed. The partial reverse active mask is removed. The oxide layer is planarized.

Abstract: Data retention of a ferroelectric transistor is extended by injecting holes or electrons into the ferroelectric transistor when power is removed. The ferroelectric FET has a mechanism to trap charge in a buffer dielectric layer or in the ferroelectric layer sandwiched between a top electrode and a silicon substrate. The state of polarization is detected before power is removed from the ferroelectric FET. Charge is injected into the ferroelectric FET to produce a first threshold voltage when a first polarization state is determined before power is removed. Charge is removed from the ferroelectric FET to produce a second threshold voltage when a second polarization state is determined before power is removed. When the ferroelectric FET is powered up again, the state of charge injected is determined. The ferroelectric FET is then polarized to correspond to a first threshold voltage when the charge state corresponding to the first threshold is determined.

Abstract: A circuit and method reduces the number of nodes that must be forced during a standby mode when using clocked latches. The circuit and method can be used for half-cycle latches and full cycle latches in conjunction with alternate power-gated circuitry, even when many stages are cascaded in a pipeline structure. The data state on a single forcing node can be passed through one or more cascaded latch stages as well as through additional circuitry. By forcing latch transmission gates to be conductive during standby mode, multiple stages can be set to a specific state, as determined by an earlier stage being set by a forcing transistor. A clock generation. circuit and method is also provided for controlling transmission gates within the latches.

Abstract: A latch circuit and method of operation improves the performance of an integrated circuit memory by adding an extra latch into the write data path. The added latch is programmable such that it either is disabled (allowing the transparent flow of data), or enabled (data flow is inhibited by extra clock). In areas of the chip where the address/control information is fast, but the data is slow, the latch is disabled to allow the data to flow as fast as possible. In areas of the chip where the address/control information is slow, but the data is fast, the latch is enabled such that data cannot flow freely and must be gated by clock information.

Abstract: A bitline reference voltage circuit according to the present invention includes a first transistor having a current path coupled between a first bitline and an intermediate node, and a gate for receiving a first control signal, a second transistor having a current path coupled between a second bitline and the intermediate node, and a gate for receiving a second control signal, a third transistor having current path coupled between the intermediate node and a source of constant voltage, and a gate for receiving a third control signal, and a capacitor coupled between the intermediate node and the source of constant voltage.

Abstract: A reconfigurable processor module comprising hybrid stacked integrated circuit (“IC”) die elements. In a particular embodiment disclosed herein, a processor module with reconfigurable capability may be constructed by stacking one or more thinned microprocessor, memory and/or field programmable gate array (“FPGA”) die elements and interconnecting the same utilizing contacts that traverse the thickness of the die. The processor module disclosed allows for a significant acceleration in the sharing of data between the microprocessor and the FPGA element while advantageously increasing final assembly yield and concomitantly reducing final assembly cost.

Abstract: A ferroelectric random access memory has a ferroelectric capacitor formed of a stacking of a lower electrode, a PZT film and an upper electrode of SrRuO3, wherein the PZT film includes pinholes, with a pinhole density of about 17 &mgr;m2 or less.

Abstract: A pre-biased voltage level shifting circuit of especial applicability with respect to those integrated circuit devices requiring a technique for converting circuit operation between differing power supply levels. In a representative embodiment, the circuit utilizes feedback to make the switching transistors faster to thereby increase the speeds of the level translation of signals based upon two different power supplies.

Abstract: A method of demand based retrieval of a data file including pages of data, in a network system having a remote host system interconnected to at least one local host system via a first communication link, and one or more end-user systems interconnected to the local host system via a second communication link. A cache buffer is maintained in the local host system for storing a plurality of data pages. Upon receiving a request from an end-user system for the data file, the cache buffer is checked to determine if one or more data pages currently referenced by the request are available therein. If so, one or more of the available data pages are transmitted from the cache buffer to the end user system. Otherwise, the referenced pages are retrieved from the remote host system to the local host system via the first communication link, stored in the cache buffer in the local host system, and transmitted to the end-user system via the second communication link.

Abstract: A multi-bank memory array architecture utilizing topologically non-uniform blocks of sub-arrays and input/output (“I/O”) assignments in an integrated circuit memory device. By using non-uniform blocks of multiple identical sub-arrays, non-uniform assignments of blocks to banks and/or non-uniform assignments of I/Os to blocks, it is possible to optimize the dimensions of the chip and the placement of the I/Os with respect to the package pads. In this manner, the granularity of the building blocks of sub-arrays is improved while the flexibility in I/O assignment is also improved leading to more efficient and flexible chip layouts.

Abstract: A high voltage transistor protection technique and switching circuit of especial applicability to integrated circuit devices utilizing multiple power supply voltages. In accordance with the technique of the present intention, the problems inherent in the amount of on-chip die area consumed and speed degradation of prior art circuit implementations are overcome by furnishing a substantially direct current voltage VHVP to the gate of a first transistor of a series connected thin gate oxide pair wherein VHVP≦VDSMAX (the maximum gate-to-source voltage of the first transistor) and VHVP≦VDSMAX+Vt (the maximum drain-to-source voltage of the second transistor plus the threshold voltage of the first transistor).

Abstract: An integrated and constantly enabled on-chip test interface for use in verifying the functionality of high speed embedded memories such as synchronous dynamic random access memories (“SDRAM”) which allows for the utilization of existing, relatively low speed, (and hence low cost), testers to perform the testing. The interface allows for the verification of an embedded memory macro design utilizing a test interface which includes the memory macro and separate on-chip test circuitry so that half-rate, narrow word, input signals from a tester can perform all memory macro operations across the breadth of a wide memory macro input/output (“I/O”) architecture. The on-chip test circuitry may also include a synchronizing circuit to minimize skew between the external clock and the data output from the test chip.

Abstract: A method of storing and accessing two data bits in a single ferroelectric FET includes selectively polarizing two distinct ferroelectric regions in the same gate dielectric layer separated by a non-ferroelectric dielectric region. A first ferroelectric region is sandwiched between the substrate and the gate terminal in the region of the source and is polarized in one of two states to form a first data bit within the FET. A second ferroelectric region is sandwiched between the substrate and the gate terminal in the region of the drain and is polarized in one of two states to form a second data bit within the FET. Detection of the first data bit is accomplished by selectively applying a read bias to the FET terminals, a first current resulting when a first state is stored and a second current resulting when a second state is stored. The polarization of the second data bit is accomplished by reversing the source and drain voltages.

Abstract: A single transistor (“1T”) ferroelectric memory cell, device and method for the formation of the same incorporating a high temperature ferroelectric gate dielectric. The memory cell of the present invention comprises a substrate, an overlying ferroelectric layer, which may comprise a film of rare earth manganite, and an interfacial oxide layer intermediate the substrate and the ferroelectric layer. In a preferred embodiment, the ferroelectric material utilized in an implementation of the present invention may be deposited by metallorganic chemical vapor deposition (“MOCVD”) or other techniques and exhibits a low relative dielectric permittivity of around 10 and forms an interfacial layer with a relative dielectric permittivity larger than that of SiO2, which makes it particularly suitable for a 1T cell.

Abstract: A computer network has a subnetwork of computers including a server, a first authentication server, a firewall, and network interconnect. This subnetwork is connected through encrypted protocol handlers and over a potentially insecure channel to a second authentication server. Some authentication requests, especially for users not authenticated in the first authentication server's database and determined by the first authentication server to be authenticatable by the second authentication server, are passed from the server of the subnetwork through the encrypted protocol handlers and over the potentially insecure channel to the second authentication server.