Abstract: A system and method for low cost testing of integrated circuit devices at their rated speed during wafer probe testing while input signals to, and output signals from, the device may be operated at a lower speed. In the exemplary embodiment disclosed, a probe pad is used to enable a special test mode. When enabled, the on-chip clock generator enables a clock frequency doubler. The frequency doubler generates a 2× frequency clock from the 1× frequency external clock signals (two 1× clock phases with a 90 degree phase shift between the two clocks). The first phase of the clock uses the CLK input of the device and the second phase uses the device's CKE input.

Abstract: A simultaneous function dynamic random access memory (“DRAM”) technique of particular applicability to DRAMs, synchronous DRAMs (“SDRAM”), specialty DRAMs, embedded DRAMs, embedded SDRAMs and the like which enables the execution of “read”, “write”, “active” and “precharge” commands on a single clock cycle. The technique of the present invention is of especial applicability to embedded memory arrays or specialty DRAMs where the number of input signals to the DRAM are not necessarily limited by mechanical component packaging constraints or component pin counts. In general, the advantages of the technique are obtained through the use of separate address fields, including bank addresses, for “read” and “write” commands, and separate bank addresses for “active” and “precharge” commands with a resultant highly parallel operational functionality.

Abstract: A data bus architecture for integrated circuit embedded dynamic random access memory having a large aspect ratio serves to reduce power requirements in the data path through the use of multiple metal layers to reduce capacitance on the data busses. The memory is divided into multiple sections with data bussing in those sections routed in one metal, or conductive, layer. A different metal layer is used to route global data across these sections to a data register located on one edge of the memory. These global data lines are double data rate and single-ended which increases the physical spacing of these lines thereby reducing capacitance and power requirements. Each of the global data lines are routed to only one of the memory sections. This results in the average length of these lines being less than the length of the entire memory, which reduces the capacitance of the lines.

Abstract: A search coprocessor card for attachment to a computer system has an interface to a host processor of the computer system and a processor. The processor has memory for its program and data, and is coupled to one or more search engine devices. Each of the search engine devices is in turn coupled to a memory for holding key tables, and is capable of searching the key tables for matching entries.

Abstract: A reconfigurable processor module comprising hybrid stacked integrated circuit (“IC”) die elements. In a particular embodiment disclosed herein, a processor module with reconfigurable capability may be constructed by stacking one or more thinned microprocessor, memory and/or field programmable gate array (“FPGA”) die elements and interconnecting the same utilizing contacts that traverse the thickness of the die. The processor module disclosed allows for a significant acceleration in the sharing of data between the microprocessor and the FPGA element while advantageously increasing final assembly yield and concomitantly reducing final assembly cost.

Abstract: A circuit and method for an integrated circuit memory incorporates a look-ahead function where refresh commands are presented to the device at least one cycle before actual internal refresh operations occur. Active cycles are executed on the same clock as the external command is applied. Active commands are unaltered and are executed on the same clock cycle as the occurrence of the active command. Active commands can be executed immediately without waiting to determine if the row address latch is to be sourced externally or internally.

Abstract: A data path decoding technique and architecture for integrated circuit memory devices and those devices incorporating embedded dynamic random access memory (“DRAM”) arrays provides an effective second level of decoding resulting in a need for routing fewer column select lines to the sense amplifiers as compared with existing designs while concomitantly providing for shortened local data lines resulting in less undesired resistance and capacitance. The technique and architecture of the present invention requires no additional on-chip area to that required by existing designs and adds no new gate delays or pass gates to the critical read data or write data paths. This is effectuated by the incorporation of an address function with the read/write enable (“RWEN”) or separate read enable (“REN”) and write enable (“WEN”) signals. Consequently, half as many column select lines need be routed to the sense amplifiers since a second level of column decoding is provided.

Abstract: A method for loading an integrated circuit FIFO at extremely high operating frequencies includes providing N logical locations, providing N+1 transparent latch stages, and providing N+1 write pointers, wherein two write pointers are contemporaneously enabled during a FIFO load operation. The method can be extended to enable three or more write pointers for even higher frequency operation.

Abstract: An automatic delay technique for early “read” and “write” memory access operations in synchronous dynamic random access memory (“SDRAM”) devices and those integrated circuit devices employing embedded SDRAM arrays. A circuit and method is provided which controls the internal column select (“Yi”) and data signals such that the column address strobe (“/CAS”) signal is allowed to go “active” in advance of that otherwise possible in conjunction with conventional SDRAM arrays. In an exemplary embodiment, the column select signals (“read” or “write”) are delayed until either the corresponding, pre-decoded column address signal or the respective column clock signal is valid, whichever occurs later.

Abstract: An arbitration method and circuit for control of double data rate (“DDR”) dynamic random access memory (“DRAM”) device first-in, first-out (“FIFO”) registers which allows the data path of the device to be functional over a wider range of system clock and delay locked loop (“DLL”) clock signal skews. By comparing the system and DLL clocks, the circuit and method of the present invention determines whether the DLL clock should be considered “faster” than the system clock, or “slower.” Functionally, it then attempts to force all cases into the “fast” condition until a determination is made that the amount of advance is now so fast, that data corruption in the pipeline might occur. Only in this case will it force the result to be “slow,” adding 1 cycle to the output control path, and thereby correcting the data flow.

Abstract: A cell generator for UTMC's gate array library of core logic cells is implemented using Cadence® Relative Object Design (ROD) software. The ROD functions use design rules to create and align ROD objects. Design rules can be specified for different foundries and technologies, or can be altered to special design requirements. ROD user-defined handles are created to facilitate internal routing and to accommodate different UTMC architectures. Hierarchy is used to minimize the ROD code, and a Cadence® SKILL Makefile generates the entire library automatically.

Abstract: An error-correcting partial latch stage includes a first pass gate having an input for receiving a data input signal, an output, and a control node for receiving a control signal, a second pass gate having an input coupled to the output of the first pass gate, an output for providing a data output signal, and a control node for receiving the control signal, an inverter having an input coupled to the output of the first pass gate and an output; and a correcting inverter stage having a first input coupled to the output of the inverter, and second and third inputs for receiving voting signals from adjacent error-correcting latch stages, and an output coupled to the output of the second pass gate. A full latch stage includes three interconnected partial latch stages. The full latch stage has a high degree of immunity from SEU events and from on-chip noise coupling.

Abstract: A pre-charge and reference voltage technique operates on a DRAM memory array in which two additional rows of reference cells are added to the array. When the array starts the pre-charge cycle, the regular word line and latch P-channel bar signals both turn off and the complementary bit line pair is shorted together. These two lines charge share to create a half way voltage level (VCC/2) that is restored into the reference cell. After this voltage is restored into the reference cell, the bit lines are fully pre-charged to ground.

Abstract: A base cell for a gate array or standard cell integrated circuit design has N and P wells organized in checkerboard fashion, each well containing several P and N devices respectively. A first of the plurality of relatively deep P regions is adjacent to at least a first and a second of the plurality of relatively deep N regions. The first relatively deep N region is adjacent to the first relatively deep P region along a first edge of the first relatively deep N region, and to the second relatively deep P region along a second edge of the relatively deep N region. The first and second edges of the relatively deep N region are perpendicular. An array of the base cells therefore has a checkerboard pattern, unlike the striped pattern of typical gate array and standard cell designs. The array of the base cells is amenable to minimizing clock parasitic capacitance when clocked inverters, including the complimentary clocked inverters of latches, are laid out at vertexes of the checkerboard pattern.

Abstract: A memory cell layout for use in a 1T/1C ferroelectric memory array includes an access transistor having a gate coupled to a word line and a current path coupled between a bit line and an internal cell node, a shunt word line extending across the memory cell that is electrically isolated from the word line and the access transistor within the physical boundary of the memory cell, and a ferroelectric capacitor coupled between the internal cell node and a plate line.

Abstract: A sense amplifier design for DRAM devices (as well as those incorporating embedded DRAM) which provides improved read and write speed without requiring the use of an extra signal line to the gate of a transistor coupling the sense amplifier latch nodes to the associated bit lines. In accordance with the present invention, an additional circuit element is added between the latch nodes and the bit lines which serves as a resistive path therebetween. Functionally, this additional circuit element serves to isolate the latch nodes from the relatively large bit line capacitance during a write operation such that the latch nodes can change state more quickly. These additional circuit elements may take the form of N-channel transistors having their gate tied to a pumped voltage level VCCP, resistors, various configurations of depletion transistors or CMOS pass gates.

Abstract: A small signal, low power read data bus driver for integrated circuit devices incorporating memory arrays which advantageously utilizes non-precharged data lines and reduced output voltage swing to reduce power requirements, tri-stateable outputs to allow several circuits to be multiplexed on the same data line and provides a buffer between the sense amplifier and the data lines to improve data line switching speed.

Abstract: A low voltage boost circuit suitable for use in a ferroelectric memory is realized implementing five N-channel devices and two ferroelectric capacitors. The voltage on a word line is boosted using charge sharing techniques in order to assure proper operation at lower power supply voltage conditions. In operation, the gate of an N-channel pass gate is boosted to supply a full VDD voltage on the bottom electrode of a ferroelectric capacitor, which capacitively couples into the word line for an efficient word line voltage boost.

Abstract: A negative voltage driver circuit having reduced current flow to the negative supply voltage source and improved reliability comprises first, second and third series coupled switching devices defining an output and intermediate nodes therebetween respectively for coupling a high voltage source to a reference voltage level. Control terminals of the first and second switching devices are coupled to a first circuit node and a control terminal of the third switching device is coupled to a second circuit node. A fourth switching device is coupled between the lower intermediate node and a negative voltage source, with a control terminal of the fourth switching device being coupled to a third circuit node. In operation, the first circuit node is activated, followed sequentially by the second and third circuit nodes, the second circuit node being deactivated substantially concurrently with the activation of the third circuit node.

Abstract: A driver timing and circuit technique for a low noise charge pump circuit of particular applicability with respect to integrated circuit devices requiring voltage levels either more positive than or more negative than, externally supplied voltages. In accordance with the technique of the present invention, the pump capacitor is driven “high” by one transistor and “low” by another. By correctly sizing the devices driving them, each transistor can be turned “off” quickly and “on” slowly and, in an alternative embodiment, both transistors may be “off” at the same time resulting in “tri-state” operation.