Abstract: A graphics processor capable of rendering three-dimensional polygons with color, shading; and other visual effects also corrects interpolation errors that occur as a result of mapping the polygon to a pixel grid display. The processor renders polygons using an Incremental Line-Drawing algorithm and features an error correction circuit capable of adjusting the initial and incremental gradient parameters for each pixel characteristic and then rendering each scan line with the proper orthogonal adjustment. The error correction circuit includes an ortho correction engine for correcting errors in the initial and incremental pixel parameters and an ortho adjust engine to accommodate overflows in the x-coordinate calculations. The processor is able to render the polygons with monotonic gradients in color, shading, depth, and other visual characteristics without interpolation error.

Abstract: A capacitively isolated input system that permits sensing of an input voltage with a below-ground value or a below-substrate voltage value. Multiple input signals are received, and each input signal is connected to cross-connected switching components. Switched output signals are capacitively connected to additional switching components and to a sensing amplifier. This system allows the sensing amplifier to receive capacitively isolated input signals and to provide corresponding output signals at voltages no lower than ground voltage.

Abstract: A discrete-time strongly cross-coupled complex bandpass modulator is disclosed that achieves the full potential of bandpass delta-sigma conversion by providing a strongly cross-coupled discrete-time complex loop filter structure with very low sensitivity to mismatches and by providing a simple scheme for correcting the effects of modulator mismatches. The complex bandpass modulator includes a plurality of non-linear resonators connected together and acting as a linear complex operator. Each resonator will act as a linear complex operator when an imaginary input signal is delayed by half a sample interval and an imaginary output signal is advanced by half a sample interval. In addition, degradation effects due to modulator mismatches are eliminated by digitally adjusting the relative gain of the real and imaginary paths following the output of the analog-to-digital converter and by adjusting the relative gain of the real and imaginary input signals.

Abstract: A static, low-power differential sense amplifier (DSA) and method includes operation of cross-linked channels having complementary differential nodes separated from ground by corresponding parallel-transistor pairs. The DSA output channels have complementary output nodes separated from ground by corresponding parallel-transistor pairs. The DSA further includes logic gates to produce a sense amplifier output. Each logic gate is driven by a corresponding complementary differential node and an opposite complimentary output node. The DSA includes transistors activating a done line under control of the complementary differential nodes.

Abstract: A full-duplex communication device includes a transmit channel, a receive channel, and echo cancellers connected between the transmit channel and the receive channel. A plurality of control parameters and status indicators are defined for both channels. The plurality of control parameters are accessed via a writable interface for controlling operations of the communication device. Typically the control parameters are modified, enabled, and disabled based on an implemented control method and based on signal conditions, including noise, echo, tone, and other abnormal noise conditions. A writable access port enables a user to request tweaking, modification, enabling, and disabling of multiple features and controls. A readable/writable access port enables access to multiple status parameters that are indicative of the status of the communication device and channel operating conditions.

Abstract: An asynchronous sample rate converter for converting a first sample rate in a signal to a second sample rate in the same signal is presented. The signal is first provided as input to an interpolator which upsamples the signal to form a signal having sample rate UFs1 where the upsampling factor U is a variable that is directly related to the ratio Fs2/Fs1. The resampler then linearly interpolates the upsampled signal to form a signal having sample rate DFs2. Finally, the resampled signal is downsampled to form a signal having sample rate Fs2.

Abstract: A method for dynamically caching display list information to an internal on-chip cache performs UV title read hit comparisons to determine whether to read display list parameters from internal cache or external memory.

Abstract: A signal processing circuit includes a main input sampling structure with an integrator operational amplifier and input lines including a switched capacitor. The input lines have switched connections to input signal lines and reference signal lines. A replica sampling structure is used in combination with the main input sampling structure to eliminate or reduce signal-dependent current that is drawn from the input signal line and the reference signal line. The replica sampler includes buffered input lines and switched capacitor of the input sampling structure but the capacitors have switched connections to the reference signal lines such that the connections have opposite polarity to the connections of the reference signal line to the input sampling structure. The replica sampler eliminates or reduces signal-dependent current from the reference signal lines. Buffering of the input lines in the replica sampler eliminates or reduces the signal-dependent current drawn from the input signal lines.

Abstract: A modem interface unit is provided for coupling a communications modem to a host processor. The modem interface unit includes a host interface for coupling to a host processor, an anlog interface for coupling to a communications modem and a digital signal processor for performing signal processing operations on modem signals as they are transferred from the host interface to the analog interface and vice versa. A memory is provided for use in moving the modem signals through the interface unit. A sleep mode mechanism is provided for discontinuing the supplying of operating current to the digital signal processor when no modem signals have been transmitted or received for a predetermined period of time.

Abstract: A process and implementing computer system in which a graphics subsystem 117 having an XY coordinate addressing system interfaces with a host computer system having a linear addressing configuration. The subsystem includes an internal graphics engine 325, a host interface bus 301 and a host interface bus master circuit 321 for initiating data fetch and write requests to the host computer system memory 109. A subsystem host-XY circuit 327, 317 processes address requests between the subsystem and the host through the host system bus 105. A host system bus master circuit 315 is included in the subsystem 117 and is responsive to the host-XY circuit 327, 317 to access the host system bus 105 and effect the transfer of requested data through subsystem queuing units 303, 307 to the subsystem host interface bus 301 from which such requested data may be acquired by the requesting graphics engine 325.

Abstract: A method and circuit to regulate a random waveform signal to ensure that the LED indicator driven by the waveform signal is visible to the human eye is provided. The method and circuit first determines whether there is a pulse occurring. If an on-going pulse is detected, the regulated waveform signal is driven HIGH for at least 8 clock cycles. If no on-going pulse is detected, the regulated waveform signal is driven LOW for at least 8 clock cycles.

Abstract: A modem interface communicates data between a computer and a modem that is coupled to an external communication network. The modem interface includes a host interface for coupling to a host processor of the computer, an analog interface for coupling to the modem, and a digital signal processor for processing the data communicated with the modem and the host processor. A memory is coupled to the host interface, the digital signal processor and the analog interface. The analog interface provides clock signals and converts data between analog and digital for communicating between the memory and the modem. The analog interface provides an interrupt to the digital signal processor to control the transfer of data from the digital signal processor and the memory. The modem interface processes data at sampling rates while the host processor processes data at rates less than the sampling rate of the analog interface.

Abstract: A device is disclosed which combines the advantages of CMOS and bipolar using an existing parasitic bipolar device. As such high on-chip density is attainable with the device along with high speed capability while maintaining low power advantages.

Abstract: An 8-input, 1-output mux-based logic module for an FPGA is disclosed. The logic module comprises five separate multiplexers connected differently in the various embodiments of the present invention. The 8-input logic module can realize a total of 2390 unique functions. A 7-input, 1-output variation of the logic module of the preferred embodiment is also disclosed.

Abstract: A logic module uses a multiplexer which can be used to configure the logic module as combinational or sequential. A sequential block comprises a flip-flop with preset and clear, and can be SR or D-type. The multiplexer is used in the feedback loop of the flip-flop, thus by choosing an appropriate select signal the feedback can be connected/disconnected.

Abstract: A method and apparatus for reducing aperture uncertainty and kick-back noise in high speed comparators is disclosed. The disclosed method is used in a comparator for comparing a first signal (INP) and a second signal (INM) and having a track mode and a regenerative mode of operation. The steps of this method are as follows. A first input current representing the first signal is switched through a first output node (OUTP) during the track mode and a second input current representing the second signal is switched through a second output node (OUTM) during the track mode. During the regenerative mode, approximately half of the first input current is switched through the first output node (OUTP) and approximately half of the first input current is switched through the second output node (OUTM). Also during the regenerative mode, approximately half of the second input current is switched through the first output node and approximately half of the second input current is switched through the second output node.

Abstract: A plasma processing system 10 for fabricating a semiconductor wafer 24 is disclosed. The system includes a plasma processing tool 12 and an RF energy source 20 coupled to the plasma processing tool 12. An optional matching network 22 may be included between the RF energy source 20 and the plasma processing tool 12. Circuitry 18 for monitoring the RF energy to obtain a measurement characteristic is also provided. At least one transducer 14 or 16 is coupled between the plasma processing tool 12 and the circuitry 18 for monitoring the RF energy. The RF energy is typically applied at a fundamental frequency and the electrical characteristic is monitored at a second frequency different than the fundamental frequency. Also included is circuitry 19, such as a computer, for interpreting the measurement to determine a condition of the processing system 10. Other systems and methods are also disclosed.

Abstract: A regulated cascode circuit with enhanced gain includes a cascode section including a common source MOS transistor (m.sub.1) of a first polarity and a cascode device (m.sub.2) wherein the drain of the common-source MOS transistor (m.sub.1) is coupled to the source of the cascode device. An input to the regulated cascode circuit is applied to the common source MOS transistor (m.sub.1) and an output of the regulated cascode circuit is developed at the drain of the cascode device (m.sub.2) across both the common source MOS transistor (m.sub.1) and cascode (m.sub.2) device. A feedback amplifier circuit (10) has its input (12) connected to the drain of the common source MOS transistor (m.sub.1) and its output (20) connected to a gate of the cascode device (m.sub.2) for driving the cascode device (m.sub.2). The feedback amplifier (10) includes a simple five transistor circuit.

Abstract: In a semiconductor device having two N type regions separated by a P type region, a channel stop is needed to prevent shorting between the two N type regions. The channel stop of the invention has oxide isolators over the two N type regions and a P+ type diffusion lying between the oxide isolators in the P type region. When the N type regions are phosphorus doped deep N- regions biased at different potentials and the P type region is a boron doped P- region, a shallow P+ boron region within the P- region acts as a blocking mechanism to prevent phosphorus from piling up at the semiconductor surface and shorting the two N- regions. The channel stop may be manufactured without adding additional steps to a CMOS process flow. The oxide isolators may be formed when the oxide isolator over the inverse moat separating the P tank and the N tank is created. The P+ region within the channel maybe formed when the sources and drains for transistors within the N tank are formed.

Abstract: A chilling system (12) has a container (20) filled with a coolant (22). A pipe (16) traverses within the container (20) and the coolant (22) to a housing (18). Fluid flows within the pipe (16) and becomes chilled through the pipe (16) upon entering the container (20) and the coolant (22). The chilled fluid enters the housing (18) chilling the housing (18) through the pipe (16). In turn, semiconductor substrate (19) in contact with the housing (18) also is chilled.